Digital IF Filter Design And Implementation Of FPGA

With the rapid development of communication and information technology,digital filter is playing a role of importantance and has been widely used in digitalsignal processing applications, such as image processing, data compression, digitaltelevision and digital communication equipment, etc. Digital is nowadays a totallydevelopment direction on wireless network optimization equipment,and itsbottleneck consentrates on digital signal processing computing capability. Atpresent, digital IF is an important part of achieving the application of softwareradio technology. A digital filter commonly has greater flexibility and stability,compared to an analog filter, making it enhanced in the realization of performanceand lower cost to achieve a better balance, and thus helping develop morecost-effective digital products of the next generation,such as wireless networkoptimization equipment particularly.Compared to ASIC, FPGA design has apparent features of more flexibility andlower cost.In this paper, the multi-carrier gsm digital IF filter is implementedthrough DDC and DUC,making use of FPGA chip features and advanced softwareanalysis and implementation tools.Firstly,the project makes full use of secondmixing technology both in DDC and DUC process,and secondly research is done onthe optimal design for channel time-multiplexing.The performance of digital IFchannel selection is improved consulting the practical project. The digital IF filtermodule is checked through simulation and FPGA hardware verification and hasbeen delivered in the real project.Several hardware and software problemsaffecting the filter module performance have been given a number of analysis andresolution. The results show that the program proposed in this paper is correct andfeasible to achieve the requirements.In this paper, the Xilinx’s FPGA, XC4VSX35F668-10device in the Virtex4series is designed to meet the requirements of engineering applications. For theGSM Digital Radio Remote System, or for the digital wireless repeator, in thetarget condition of good digital filter performance,the design has the capacity ofselecting12frequencies, including uplink and downlink data trains,so as to say, atotal of24carrier frequencies in a single board. Specific to each carrier frequency,regarding the resources of a single-channel down-conversion and up-conversion on the chip, the total occupation of the main resources slice does not exceed700;DSP48dedicated hardware multiplier is not more than7; RAM16B module numberof not more than7. With a single chip to meet the needs of the engineering, thedesign reaches a relatively advanced level in the domestic application of the sametype of chips, considering the capacity and the cost of a single carrier frequency ina chip. Therefore, the research on the design of digital IF filter of a new generationin this article provides a certain degree of referential significance for IF digitalprocessing on FPGA related products in communication.In this paper the IF filter designed makes full use of second mixing technologyboth in DDC and DUC process, enabling us to reduce the rate of data processingwhile meeting the bandwidth requirements,thus making multi-carrier frequencyselective processing more reasonable. The flexibility and efficiency has beenimproved in the filter implementation using the IP module and RAM plus MACmodule combined.While using the FIFO for ADC and DAC data interfaceconversion in clock domain, the stability of the hardware products testing thenreaches a high degree.