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Design And FPGA Implementation Of Digital Intermediate Frequency System In TD-LTE Base Station

Posted on:2016-08-06Degree:MasterType:Thesis
Country:ChinaCandidate:L ShiFull Text:PDF
GTID:2298330467991746Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
The vast coverage of Base Station and development of LTE multi-frequencymulti-mode era accelerates development of new technology such as Software DefinedRadio(SDR).Now intermediate frequency signal digitalization becomes the prevalentchoice in Software Radio,thus,Digital Intermediate Frequency(DIF) technique becomeones of the core technologies of SDR.As a part of Remote Radio Unit,DIF is the keyfactor connecting radio signal and base band,it contains digital up converter(DUC) anddigital down converter(DDC).The main effect of DDC is to change signal from highdata flow to low data stream after digitization of A/D converter and as a result,improving channel demodulation in BBU. DDC is mainly made from both digitalquadrature mixing and decimation filter.On the contrary,DUC is used to improve theresolution of the base band signal in order to reduce the quantization error andcomplexity of analog filter design after D/A converter.DUC is mainly made from bothinterpolation filter and peak clipping. The importance of DIF is to keep signal qualityinvariable while this transition.This paper completes the DIF system design which is based on the FPGA afterdoing relevant theoretical research.DDC/DUC algorithm,interface with intermediatefrequency simulation part and BBU are implemented in FPGA. In DDC part, eachimportant module, including orthogonal mixing circuit, CIC interpolationfilter,half-band filter and FIR filter is analyzed and algorithmic designed respectively. InDUC part,zero intermediate frequency technology, interpolation filter,peak clippingtechnology is analyzed and algorithmic designed respectively.In interface designpart,FPGA with ADC/DAC interface,CPRI protocol and SERDES interface is analyzedand designed respectively.Besides,this paper also introduces hardware related designsuch as power design and devices selection. At last,this paper describes the hardware implementation based on simulationverification of the key module.Then,have a data path test on uplink and downlink usinga single signal to verify the feasibility of system design.
Keywords/Search Tags:digital intermediate frequency, digital up converter, digital downconverter, FPGA
PDF Full Text Request
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