Research Of Automatic Test Method On Telemetry System

Telemetry system is widely applied in military missile tests, the generation of the system provides an effective accomplishing means for our country’s military missile test, and with the application of telemetry system expands, telemetry system has become more complicated, according to the telemetry system test requirements are also increasing, therefore, according to specific testing methods, this paper has designed a set of automatic test system specifically for a certain military telemetry system On the premise of to provide accurate test results, through the optimization of system design, reduced the degree of difficulty of testing each module in the telemetry system, using automated means, further shorten the telemetry system test cycle, thereby indirectly improve the level of our country’s military missile test.This paper elaborates the topic background, research significance, the definition of telemetry system and the automatic testing system, at the same time, this paper examines the research situation at home and abroad in view of the automatic test system through the literature books that provides reference for the research of this paper. Then, this paper makes a detailed project design about the design of automatic test system. This paper determines the early stage of the functional requirements and technical indicators, according to the incremental mode of development and requirements analysis, designs of system hardware and software architecture after the completion of the architecture design, finishes system planning, system interface design, upper and lower position machine software and hardware implementation, etc.In this paper, the hardware design is mainly aimed at a lower computer, the lower computer is relative to the IPC(Industrial Personal Computer), the design concept of lower computer is in accordance with the embedded design. This paper uses2C20FPGA chip, which is produced by Altera company, as the main control core of lower computer, by embedding Nios II soft core CPU, it gives the FPGA chip with SOPC design features. For important bus unit in this set of automatic test system, this paper designs a TCP/IP Ethernet, CAN and RS485hybrid bus, the fact proved that the hybrid bus design laid the link foundation for the data flow of efficient and reliable transmission. In particular, the network communication in lower computer is based on μC/OS-Ⅱ NicheStack embedded network protocol stack, this paper implements the Nios Ⅱ network interface design oriented NicheStack, and the ethernet controllers (dm9000and enc28j60) work properly, in order to not lose the generality, this paper puts forward the architecture design idea related to the first phase of the project, the architecture design is based on the accumulation of practical experience of multiple laboratory projects in early stage, and it’s able to withstand the actual reasons. The upper and lower computer software use C#and C language to realize respectively, using object-oriented and process-oriented, the two typical programming language, to realize the logic of this system, in order to decrease the difficulty of maintenance and increase the possibility of transplantation, in practical application, the software uses some design patterns and programming skills in process of writing, which increases the administrative levels of the code, high cohesion and low coupling. Architecture design makes the parallel design, maintainability, portability and rapid development become possible.In the last, the physical display of automatic test system is given in this paper, and this paper analyzes the test result, and describes the details in this system that can be optimized.