Analysis Of The Trustable Arithmetic Subtractor Circuit Design

Integrated circuit is the core and foundation of the informationtechnology industry and the important guarantee of promoting theInformationization of the national economy. Arithmetic subtractor circuitis the important basis for integrated circuits, so trustable analysis andverification of arithmetic subtractor circuits design is an important link inintegrated circuits design and analysis. Arithmetic subtractor circuitgenerated the time delay in the working because of the impact of signaltransmission. Delay makes the circuit in clock cycle sample the outputresults and the theoretically correct logic circuit output have errors, whichcan result in abnormal operation of the circuit and even crash.As the basic unit circuit, full subtractor is the core of the circuit CPUoperation, whose speed and power consumption performance directlyaffects the overall performance of the integrated circuits. With thedevelopment of information technology, consumers for low-power,high-performance and highly integrated constant pursuit of circuit designfor more performance factors need to be considered in the process, suchas delay, power consumption, trustable, leakage, etc. This paper mainconsider the reliability of circuit design, especially for arithmeticsubtraction circuit delay led to of output errors problem, from formal ofangle portrayed the arithmetic subtraction circuit. The continuousmodeling of discrete signals in circuit, respectively established outputerrors model and energy consumption model, through geometryprogramming and the convex programming theory on circuit of modelformal analysis and trustable measure, improve the design of arithmeticsubtraction circuit credibility.