| With the increasing capacity and power processing of FPGA, logic resources in a singleFPGA chip have exceeded4million gates. Because of the rapid development and parallelcomputing features of FPGA, it is used more and more in many solutions, especially inhigh-definition image processing and highly parallel big data computing. Traditionally, FPGAis design to be a coprocessor with fixed feature.There is not fully utilize the max advantagesof FPGA-Field Programmable.The focus of this article is to study the dynamic FPGA configuration mechanism anddesign a hardware/software platform for machine vision applications to verify the applicationof the dynamic configuration mechanism. At the system running, program configure theFPGA via serial port and manage the FPGA resource. Dynamic configuration can achievemultiple applications time-sharing the FPGA, improve the utilization of FPGA, and reducethe difficulty of development.According to the needs of dynamically configured and machine vision applications, weAnalyze all mode of FPGA configuration, design and implement the hardware platform. Thehardware platform is composed of two parts. One part is CPU S5PV210based on the ARMCortexTM-A8. Another part is Xilinx XC6SLX150T FPGA. The CPU control FPGA state,through a set of GPIO. The CPU through the SPI interface to configure FPGA that in passiveserial configuration mode. Communication between the CPU and the FPGA via the CPU’sEBI (External BUS Interface).EBI is connected to the FPGA internal dual-port RAM.Peripheral interface is designed for imaging applications. FPGA status and assignment modelcalculation, the package FPGA dynamic configuration API interface.Final, a reconfigurable hardware structure to accelerate KNN (K nearest neighbors)based on Haar wavelet transform is proposed. This structure is used in as the textureclassification module for a high-quality hardware contour detection accelerator. Weimplement the application on o platform previously designed. This hardware structure is ableto fit in computing with different dimensions through changing components of the wavelettransform. It can also meet different requirements for logic resources utilization and timeperformance through adjusting hardware parallelism when the specific dimension isconsidered. When algorithm running to classification stage, program calls KNN acceleratorthrough dynamic configuration API. Then FPGA return the result of classification to completethe subsequent calculations on CPU. This process reduce half time of classification.Experiments show that the design of hardware and software systems can correctlycomplete the FPGA configuration and FPGA dynamic resource management. The time ofdynamically configuration is1.550seconds. In FPGA applications without frequentconfiguration, this hardware and software platform for FPGA dynamic configuration andmachine vision can improve system efficiency. |
