Research And FPGA Verification Of Image Scaler In The Digital HDTV SoC Chip

With the popularity of digital television, the customers have more and morerequirement on the quality of display image. Image scaler, the key technology toimprove the quality of the image, becomes more and more important. Thus, the imagescaling algorithm becomes a hot spot.Interpolation algorithm is the common one of traditional image scalingalgorithms. The common interpolation algorithms, as follows: Nearest neighborInterpolation algorithm, Bi-Linear Interpolation algorithm, Bi-Cubic Interpolationalgorithm, etc. The traditional algorithms consume less calculation resource, howeverwith lower effect and some bad results such as: the detail jaggy phenomenon, etc. Inorder to eliminate the fuzzy edge and jaggy phenomenon, the interpolation algorithmsbased on edge detection appear.One edge detection algorithm is introduced in detailin this paper. We analyzed the deficiency of the existing algorithm, and improved it.First of all, make the direction judgment more accurate with increasing the directionof edge detection; Secondly, achieve the image non-polarity zoom by using polyphasefilter; Finally, adopt a de-ring algorithm in the process of image scaling to remove theringing phenomenon.According to the improved algorithm, this paper introduces the image scalinghardware implementation. Firstly, introduce the overall architecture of the imagescaling and divides different modules. Secondly, analyze the structure of the keymodules, such as: the edge detection interpolation module, the vertical scaling module,the horizontal scaling module, etc. Finally, depict the structure of de-ring module.The last part of this paper introduces the simulation and verification of theimproved image scaling algorithm, which includes two parts: one is the functionsimulation; the other is the FPGA implementation. Function simulation mainlyvalidates the correctness of the code, this paper introduces the whole verificationplatform and the simulation results. FPGA implementation is to verify the hardware circuit, improve the success rate of the chip, and reduce design risk. Throughfunctional simulation and FPGA validation, it proves the circuit design is correct andthe improved image scaling algorithm is available.