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Research And Design Of Image Backend Processing Module Applied To LCD Scaler

Posted on:2008-06-27Degree:MasterType:Thesis
Country:ChinaCandidate:X GuoFull Text:PDF
GTID:2178360272469342Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The LCD Scaler is an image-scaling chip integrated in the LCD solution system. The Scaler translates the input images which have different resolutions to a fixed resolution images, and then display on Liquid Crystal Display. Due to the limitations of scaling algorithms, distortion of signal processing, and restriction of display devices within a LCD display system, the quality of output image becomes worse. The image backend processing module design, aiming at compensate the image quality, is detailedly discussed in this paper. Moreover, the image backend processing module can be used in other image processing systems as an IP core. It mainly contains two parts: image enhancement and image colour enhancement. The first part includes sharpness, contrast enhancement, brightness adjustment and gamma correction, while the second part performs image halftoning.Based on the research and analysis of functions and architecture of LCD Scaler in LCD display system, we presents a front-end design of image backend processing module and FPGA verification with Top-Down design topology. In detail, we discuss the image backend processing module architecture, algorithm selection, VLSI implementation and the FPGA verification. When discussing the image colour enhancement module design, we propose an improved dynamic Bayer dithering algorithm with time-varying dithering matrix, which can effectively eliminate the blocky effect brought by the traditional static Bayer dithering algorithm. Furthermore, we discuss the objective image quality assessment based on Human Visual System (HVS), and compare it with the traditional methods. Then, analysis and comparison are performed between different halftoning techniques with this objective criterion.In this dissertation, the image backend processing module is described with Verilog HDL. The functional simulation and FPGA verification are performed by using EDA tools. A detailed discussion of the FPGA verification environment is presented. From the results of logic and functional verification the proposed image backend processing module can meet the requirements of the LCD Scaler system.
Keywords/Search Tags:Scaler, Image enhancement, Halftoning, Image dithering, Error diffusion, Human Visual System, Image quality assessment
PDF Full Text Request
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