Algorithm Research And Hardware Implementation Of Image Scaler In The Digital TV Soc Chip

Due to the extensive application of digital TV soc chip, image scaling module isthe key technology in the digital TV soc chip, so the scaling of images has deepscientific and economic value.This paper mainly discusses the module of image scaler in the two aspects. Oneis the study on image scaler algorithm. The two frequently-used image scaleralgorithms are illustrated and studied, based on image scaler theory. Bi-LinearInterpolation algorithm consumes less calculation resource, however with lower effect.Meanwhile, Bi-Cubic Interpolation algorithm provides a better scaling effect, withhigher calculation hardware requirement. Considered the above-mentioned situation, aimage scaler algorithms based on polyphase filter is introduced. The most obviousfeature of image scaler algorithms based on polyphase filter is that its characteristic ismore approaching to ideal low pass filter. However the image processed by the filterwill have the effect of ring and jag. So dering and dejag is introduced in the study.The other part of study is to introduce the hardware implementation structure ofthe image scaler module, based on polyphase filter. The utilization of the hardwareresource is mainly considered in the implementation of the entire module. Under theconsideration, Specially, in the design of horizontal direction, Eight multipliers and anadder are spared. The design of image scaling module hardware implementation isfeasible and synthesizedThe last part is the simulation and verification of the image scaler designed.Firstly, the total module is functional simulation by Modelsim software.Secondly,FPGA is applied to system-level verification. Based on above verification mentions,the image scaler module is available.