Design Of High-speed Multichannel Flash ADC And Analysis Of Substrate Noise Coupling

Analog-to-digital converter (ADC) is a very fundamental and key part to nearly allkinds of electronics. The applications cover a wide range requiring different resolutionto different sampling rate. And high-speed ADC plays a important role in data readingof digital communication.Simultaneity, owing to the development of large scale integrated circuits, andcontinually increases of integration and speed of circuit, noise current generated in thecircuit can propagate to the sensitive circuit through substrate. In order to improve thereliability of manufacture, this problem attracts more and more attention from circuitdesigners, and be considered during the process of circuit design.This thesis consists of two parts. The first part focuses on the design of a highspeed multi-channel Flash ADC in180nm technology, resolution of8bit, sampling rateis256MHz. The input works in the way of multi-channel, and deal with signal at thesame time of64channels, the bandwidth of signal in each channel is2MHz, samplingrate is4MHz, and finally achieve256MHz. For the purpose of reduce hardwareconsumption and input capacitance, capacitive interpolation is applied in the thesis tocut down the number of inverting amplifier. Meanwhile the application of three-stagepipeline chopper-amplifier can increase the speed of Flash ADC.The second part analyzes influence that substrate noise impact on the circuitperformance in high speed circuit, the method of three-dimensional grid is applied insubstrate modeling based on lightly doped P-substrate, substrate is divided into manycubes and each cube is equivalent to parallel resistor and capacitor. At the same time,coupling noise is also caused by jitter in the network of power/ground supply, so it isnecessary to establish models for them. The above models are applied in simulation ofFlash ADC, do quantitative analysis on changes of circuit performance due to substratecoupling noise.