Research Of Substrate Noise Coupling In Mixed-Signal IC's

As IC design and technology continuously advance, hundreds of millions transistors can be integrated on a single substrate where digital, analog and RF circuits with clock frequency of several gigahertz exist. This improvement has commenced a new era of system on-chip and package on-chip, thoroughly changing the conventional comprehension regarding noise in complex ICs. Noise generated from digital circuits will transfer to sensitive analog/RF circuits through substrate, which can deteriorate performance of analog/RF circuits, even cause failure of the whole IC. Hence, substrate-coupled noise has become one of the most important issues in mixed-signal IC design. In this dissertation, substrate noise in mixed-signal circuits is studied and analyzed.Due to different characteristics between light-doping and epitaxal substrate, distribution of current will be greatly influenced. First, two different types of substrate are modeled respectively, and the impedance matrix of multiple contacts is provided on the basis of two contacts. Meanwhile, expressions of impedance with respect of technology parameters and geometric size are also deduced. Second, principle of substrate noise coupling is analyzed considering that jitter of power supply and ground is the main source of substrate noise. Third, an approach to accurately evaluate worst noise of power supply and ground is proposed, based on the condition that power supply/ground distributed networks have inductors and decoupling capacitors.In mixed-signal ICs, there are a great number of switches operating simultaneously, pumping much current from power supply, which will accordingly produce enormous noise. This dissertation advances a superposition technique to estimate the relation between ground noise and substrate noise and provides corresponding expressions. Concerning single and multiple inverters, relevant equivalent circuit model of substrate-coupled noise is proposed, along with analysis of the impact of switch number, rising time, decoupling capacitors and parasitic inductors on noise. Finally, simulation is performed in 0.18um CMOS technology and results match previous-mentioned equations well.Several effective techniques of lowering down substrate noise is raised at the end of this dissertation.