Design And Implementation Of Digital Visual Iterface (DVI) Transmitter

Digital Visual Interface (DVI), proposed as an excellent interface standard,satisfies people’s needs for high resolution and refresh rate of display devices. Incomparison to traditional simulation display equipment, it further reduces the cost offlat panel display with stronger display performance and stability. Therefore DVIhas now been one of the most widely adopted interfaces in modern digital displaytechnology.Based on interface communication protocol of DVI, this thesis provides a detailedintroduction and analysis to the basic electrical link of DVI–TMDS (TransitionMinimized Differential Signaling) technology, and succeeds in designing a physicalcircuit for DVI interface transmitter. The input clock frequency of the circuit is set torange from25MHz to165MHz with the data transmission rate of high-speed seriallinks of ranging from250Mbit/s to1.65Gbit/s so as to reach DVI standard1.0.To solve the problems of wide input signal frequency range and high data transmissionspeed, this thesis has done researches and made innovations in the following aspects:1. In-depth study of DVI1.0protocol specification is made to propose adefinition of the system architecture of DVI transmitter and categorize the functionmodules of DVI transmitter.2. A charge pump phase-locked loop to generate the decuple double-frequency ofclock signal is designed. The theoretical guidance for the parameter setting of modulesis established on the analysis of the mathematical model of phase-locked loop and theapplication of Simulink tools to modeling and simulation. The charge sharing issues areresolved through the adoption of "bootstrapping circuit" to improve the charge pumpcircuit. The cross coupling delay unit is used to produce quick and ideal full swingdifference output to improve the triple ring vco circuit. The simulation results show that,with the input signal ranging from25MHz to165MHz, the locking time ofphase-locked loop circuit is less than2μs and the peak-to-peak value of jitter noise testis less than2.5%.3. A drive circuit for high speed serial data transmission is designed. Simplifiedmain drive circuit of current mode is proposed through the comparison of the structuresof different interface standard circuits, which results in the differential signaltransmission with low swing (400mV~600mV) required by the DVI1.0protocol andlink bandwidth of1.65GHz required by the design. The performance of level switchcircuit that completes conversion from the kernel domain with1.2V voltage to theexternal transmission circuit domain with3.3V voltage is achieved, which reduces theeffect of electromagnetic interference to transmitting signals and satisfy therequirements of high frequency signal transmission. 4. The overall layout design of the circuit is completed using SMIC CMOSprocess with0.11μm、1P8M (single polysiliconlayer, eightmetal metal) and1.2V/3.3Vmixed signal with the chip area being121.66μm×116.16μm.