Design Of Hardened Memory Against MBU Based On Orthogonal Latin Square Codes

Due to the continuous development of integrated circuit technology，the size ofsemiconductor devices is gradually reduced and the distance between the adjacentmemory storage unit becomes more and more close. Multiple bit upset (MBU)caused by one radiation event increases significantly and has a serious impact onmemory reliability. How to mitigate the MBU in memory becomes a researchhotspot in hardened SRAM field.Based on the deep study of the characteristics of MBU in different sizememories, in a view of the multiple errors correction code and correction codeconstruction, this paper proposes a design of hardened memory against MBU basedon Orthogonal Latin Square (OLS) codes, using the unique structure of OLS codeand the module characteristic with the design of memory fault safety.Firstly，this paper constructs two codes based on the modularity of OLS. One isOLS code which can correct multiple errors and the other code has the ability ofcorrecting two adjacent error through the structure optimization of the OLS.Secondly, two codes’ encoders and decoders are completed. Then the concurrenterror detection circuits of these encoders and decoders are designed based on thelogical prediction. Finally, the overall design and layout design of fault safetymemory are completed.Through the establishment of memory fault injection platform using theMemory-Compiler, the function verification of memory against multiple bit upset dis finished. Establishing the mathematical model, the Mean Time to Failure (MTTF)as an index is used to evaluate the reliability of the hardened memory. In the SMIC180nm and90nm conditions, the hardened circuits are synthesized and the layout ofthe memory is designed. The results show that the proposed design can mitigate theMBU in different size memories and has the obvious advantage in performanceindex compared with other codes.