Study On Defects Detection In IC Interconnect And Effect Of Defectsw On Circuit Reliability

With the rapid progress in science and technology, the semiconductor industry has been developing rapidly accordance to Moore's Law in the past 50 years. IC (integrated circuit) technology is developing toward the goal of miniaturization, high-density, high reliability, long life and high yield. Feature size of VLSI (Very Large Scale Integration) process technology has reached the 32nm. Silicon wafer size increases from less than 1 inch to 18 inches. The continuous decrease of feature size makes more small defects which increase the product failure and decrease the circuit reliability. Defects in IC process have become a major obstacle to yield. In IC manufacturing, if defects can be detected earlier and more accurate, it will help to improve the process and yield. Finding out the product defects or picking out the failure products will save the manufacturing cost of IC chip. Therefore, defects study of the IC is very improtant. In the IC yield studies, defects research is the key technology. It is also one of the core issues in IC manufacturability. In this dissertation, a large number of real defects are obtained from the IC. IC defect detection, feature extraction and classification and its influence on signal integrity and MTTF (Median-Time-To-Fail, MTTF) of IC are studied in detailed. The main contribution and innovation are as follows.In the thesis, a large number of real defect images are collected from the 0.18μm process line. The defect images of a different color space representation are investigated. In order to satisfy the defect detection demand of color image and gray image and decrease the calculation, the image model from RGB (Red, Green, Blue) space is converted into HIS (Hue, Saturation, Intensity) space, and then the image of HIS space is transformed into gray image. In this way, not only the defects from image can be distinguished clearly but also the processing speed of the defect detection can be greatly improved.In the thesis, two different defect detection methods-IC image defect detection based on spectral subtraction and defect detection of IC wafer based on two-dimension wavelet transform are presented. IC defect detection based on spectral subtraction can extract a standard image from three defect images. What's more, the algorithm complexity of spectral subtraction detecting defect is close to that of Fourier transform. After obtaining the standard image, the speed and accuracy of detection can be greatly enhanced by the detection method presented in the dissertation. Using the image gray-scale matching technology, impact of illumination on IC defect detection is solved. IC defect detection experiments demonstrate that spectral subtraction is fast and accurate for defect detection in IC image, and the method is of high robustness for illumination. Defect detection of IC image based on two-dimension wavelet transform is also presented in the thesis. Defect detection speed and accuracy can be greatly enhanced in wavelet space because small difference can be detected easily. The advantage of the method is of its accuracy and high robustness for illumination.Base on the defect detection,35 features of the defect which are from the point of the defect size, shape, position, self-gray feature, defects around the gray feature, features relationship etc are described in detail. At the same time, the specific mathematical expressions of the 35 defect features are given. In vestigation of the defect features in the thesis lays the foundation for further study of defects.Defect classification methods that based on BP (Back Propagation) Neural Network Defect Classification and defect gray and the change number of boundary gray are presented. Using the methods, defects can be classified into four types:short circuit defect, open circuit defect, hole defect on the foreground and redundancy defect on the background.12 features are picked out from 35 features in BP network classification. The experiments have proved that the classification method proposed in the thesis is faster and has higher accuracy. In the method defect gray and of change number of the boundary gray, the defects can be exactly classified according to the information of defect gray and surrounding gray changed. Firstly, it does not need prior information or feature information of defect and complicated classification technology. Secondly, the method does not need the defect samples. Thirdly, the method does not need information of defect feature. Experiments have proved that the classification method proposed is simple, novel, fast and accurate.With the development of IC technology, more and more interconnect layers, higher and higher clock frequency of IC devices, signal integrity issues become more and more important. In the thesis, the signal crosstalk due to redundant object defect of adjacent interconnects has been studied. The defect has been seen as a signal model of interconnect. The signal crosstalk of remote and near-end has been investigated. The method can be used to calculate the influence of defect on crosstalk quantitatively. The signal reflection of lose object defects and redundant object defects of interconnect lines are investigated in the thesis. The signal is reflected at impedance discontinuity, which is caused by the defects of the interconnect line. This new method can also be used in the testing equipment to detect interconnects defect and improve reliability of IC.In the thesis, influence of lose object defects on electromigration MTTF for six-layers copper interconnect is investigated. The temperature model with defects of each interconnection layer and Median-Time-To-Fail model of defects in different interconnection layers are presented respectively. Therefore, the defect influence on electromigration MTTF of copper interconnect can be calculated quantitatively. Based on the physical model, the temperature and the MTTF of copper interconnect can be calculated accurately, which can be used as an effective guide to IC designing and manufacturing. Abrasive particles in CMP (chemical mechanical polishing, CMP) of copper interconnect can induce dishing defects, which cause interconnect damage and impact MTTF of copper interconnect. The thesis analyzes the defects induced by CMP and presents the temperature model and MTTFmodel of copper interconnect with defects. If the ratio of interconnect thickness and effective interconnect thickness is close to 1, defects induced by abrasive particles have little influence on MTTF. When the ratio of interconnect thickness and effective interconnect thickness is far away from 1, the dishing defects induced by CMP have serious impact on the MTTF of copper interconnect. Based on the proposal physical model, temperature and lifetime of copper interconnect are calculated accurately, which can provide as the guide to adjust parameters in CMP process.