Research On High Frame Rate DMD Driving Technology Based On FPGA

The visible target simulator can simulate the target and background. Theexperiment condition can be exactly controlled and repeated in the lab, making thedetector system can be tested in the lab. So, the number of outdoor experiment canbe decreased in a certain extent. In addition, the development cycle of the detectorsystem can be greatly reduced, and the number of expenditure can be saved.Digital Micromirror Device (DMD) features relative high contrast, uniformity,stability and high frame rate compared with LCD and CRT. Especially, its advantageof relative high frame rate makes it become the first choice of target simulators asdisplay part. The higher target simulator display frame frequency is, the shorterintegration time the matching detector will be used. In the experiment of detectinghigh moving target, the working frequency of the detector is very high. Usually, thedetector requires target simulator providing twice itself working frequency inlaboratory simulation experiments. Because of DMD modulation plan, display framefrequency of traditional simulation system based on DMD is below the frequencythat high-speed detector demands. So blinking and stripe will appear in thesimulation experiment, and desired results can’t be achieved.This thesis raised a high frame rate driving technology of DMD based on FPGA.First, through analyzing advantages and disadvantages of spatial gray-scalemodulation, frame gray-scale modulation and PWM (pulse width modulation), thisthesis selected PWM to modulate DMD for its features of high resolution and highframe rate among the three gray-scale modulation methods. Second, factors onrestricting DMD display frame rate further improving were found, in the aspect ofDMD structure and operation timing. Aiming at the restriction factors, this thesis putup with two schemes. In the first scheme, image data were divided into four blockswith image shift, then loaded to DMD in sequence. In the second scheme, this thesisreduced base time of PWM and adopted “Block Clear” compensatory measure.Compared to the first scheme, the second scheme was chosen，and theoreticallymakes DMD display frame rate up to464.8Hz when DMD displays8-bit grayscaleimage.Finally, a DMD simulation system based on FPGA was built in the lab andcorresponding improvement scheme was used to control DMD. Through framefrequency test, it proved its display frame rate was up to467.2Hz in this simulation system when DMD displays8-bit grayscale image. Illumination test indicated thatthe image brightness in high frame rate decreased little compared to the traditionalmodulation scheme for DMD display image brightness.