The Research And Design Of Optical High-radix Switch Chip

With the development of the performance of high performance computer(HPC)systems,the number of compute nodes in the HPC increases rapidly,which makes the scale of the interconnection network in the HPC increased.In order to guarantee the performance of the interconenction network and decrease the hop count and transmission delay of the packets in the network,high-radix switch chip,determines the power and cost of the network has became the key component in the next generation HPC systems.Due to the limitation of I/O bandwidth,buffer resource and the difficulty of the layout of wires on the chip,The traditonal electric network can not satisfy the demand to design a switch chip with too much ports.On the other hand,silicon photonic network has the advantages of high transmission speed,low power consumption,high bandwidth and low signal crosstalk.In addition,the 3D integration technology can integrate multiple layers on the same chip,the above new technologies provide a new method to design a scalable high radix switch chip.With the help of new technologies such as silicon photonic and 3D integration,this thesis tries to overcome the bottlenecks of electric switch chips in throughput,delay,power consumption and scalability.The primary contributions and innovations of this thesis are as follows:1.Proposing the high performance high radix switch architecture based on silicon photonic and 3D integration(Chapter 3)with the help of silicon photonic and 3D integration technology to overcome the bottleneck of electronic network,this thesis proposes and explores a novel multiple layer optical high radix switch architecture for 3D integration called Graphein.The proposed3 D high-radix switch chip combines low cost photonic crossbars on multiple photonic switch layer to guarantee the the throughput of the switch network and logic modules in button electric port layers to reduce power dissipation.The throughput analysis based on the speed up model indicates that the proposed architecture has an ideal throughput of 100%.Experimental comparisons also indicate a strong motivation for considering Graphein for future high radix switch chips as it can provide high throughput for every port and fairness for all packets.2.Designing the hierarchical arbitration in optical network on chip based on resource reservation with QoS support(Chapter 4)This thesis proposes a fast hierarchical arbitration based on multi-level QoS support in optical NOCs.To realize the Max-delay guarantee for every packet and the Minbandwidth guarantee for every queue,the proposal designs the interconnections of the nodes with multi-priority data buffer queues.This thesis also introduces a centralized two-stage arbitration scheme,and guarantee the fairness of the network by the arbitration information exchanging between request nodes and arbiters,and improve the throughput to 100% based on resource reservation that With the FOAC and its reasonable layout.The novel design has obvious advantages in fairness,delay and hardware consumption compared to the previous works.3.Developing the scalable high radix switch chip based on high bandwidth memory(Chapter 5)This thesis develops a multiple port optical switch die with the help of high density,high bandwidth memory.After ameliorate the die by adding an inter-die I/O agent,This thesis also integrates multiple dies to a single chip by 2.5D integration technology and extend the switch architecture to 128 even 256 ports.The realizing of the microarchitecture of the memory control module and inter-die I/O agent shows the date transmission process and also indicates the scaliability of the chip.The simulation result also shows that the high radix switch chip based on multiple dies has advantages in power,throughput and hardware cost.4.Building the power loss and reliability analyze model for Graphein architecture(Chapter 6)This thesis proposes the analyze models of SNR,trimming power and process variation power due to the process variation and thermming sensitivity of the silicon photonic device for Grahpein architecture.This thesis also uses extra channels to decrease the trimming power and uses redundant rings to decrease the PV power of the optical network.This thesis also proposes two layout schemes of the rebundant rings to improve the efficiency of power optimization.The SNR analyze model shows that the greater channel spacing has great advantages to decrease the static power and increase the SNR of the optical network.