Design And System Verification Of IP Core For Multipoint Communication Protocol Controller Based On Serial Bus

With the continuous development of space communications technology, FPGA technology plays an increasingly important role, and the IP core of FPGA has the characteristics of using flexible, highly configurable, functional stable, and good security and low cost, are widely used in many communications regions. We can see that the design of IP core is very important for the function of the system to build. This paper is mainly about the design of IP core and system verification for serial bus multi-point communications protocol to ensure that the master and slave IP core have the good multi-point communication control functions. Multi-point communication protocol controller IP core design and system validation work which is described by this article is divided into FPGA logic design(master, slave), package interface design, hardware and cable design of the verification platform, interface driver design, software design of the verification platform and overall joint test.Among these design, the hardware of verification platform design a "One master Five slave" model to verify the correctness of IP core functions, namely the design of the hardware has one host machine(FPGA board card and PC) and five slave machines(FPGA board) hardware platform. Inside the host machine, the FPGA board card and PC motherland are connected by the PXI interface, and the host machine is connected with the slave machine via RS485 serial bus is to meet the multi-point communications physical layer architecture. The design of the interface driver is mainly to solve the interface communication problem between the FPGA board card and the PC motherland inside the host machine. The interface driver is PCI9054 driver for PXI interfaces. FPGA design of IP core is divided into the package interface design and the internal logic functional design. Among this, the interface design of the host machine IP core provides the communication bridge of the FPGA inside the host machine and the motherland and five slave machines; slave machine interface provides the communication bridge of the host machine and the slave machine. Bit address label inside The internal logical functions of IP core include identification of address index, CRC check, send commands and receives the response, the function code presentations of the multi-point communication protocol. Software design of the verification platform uses MFC to make PC software for IP core functional testing, the software includes the function of sending commands, receiving and displaying, etc.After the design and the verification of all aspects of the verification platform and overall joint tests, we find that the multi-point communication protocol controller IP core design functions properly complete, flexible configuration, good security, and it achieves a multi-point communication function between devices well. The IP core provides convenient conditions for the future FPGA related design, as well as provides a good protection for the satellite payload data communication networks multipoint communication has contributed for space communications technology and has great significance for many communications technology achievement.