Research Of TDC Techniques For T0 Detector In The External Target Experiment Of CSR In HIRFL

Heavy ion physics is an important field of nuclear physics, and the heavy ion accelerators are the most vital experimental facilities to heavy ion physics research. Heavy ion research facility in Lanzhou (HIRFL) is the biggest heavy ion experimental facility in China. Since it was built, many influential achievements were made, such as synthersizing of new nuclei, mass measurement of nuclides, heavy ion cancer therapy and so on.The main research in HIRFL CSR (Cooling Storage Ring) external target experiment are nuclear equation of state research, radioactive ion beam physics research and hypernuclei research. TO detector is one of the key components in the External Target experiments, and it consists of multiple multi-gap resistive plate chambers (MRPCs). TO detector is placed at the most front area of CSR external target experimental system. After the beam hits the target, secondary particles are generated, among which some particles pass through the MRPC and interact with the gas inside it, generating electronic signals. Through precision measurement of these signals, time information when the beam hits the target can be obtained, which is utilized as the "start" of other detectors.This dissertation focuses on research of time-to-digital conversion techniques, which is expected to be used in TO detector readout electronics, and a time-to-digital conversion moudule was successfully designed. The dissertation is arranged as follows:In Chapter One, the HIRFL CSR external target experiment was overviewed, while the architecture of TO detector system and requriements on the readout electronics were introduced.In Chapter Two, popular time-to-digital converter (TDC) implementation techiqneus were introduced, which can be categorized into two types:analog TDCs and digital TDCs. Then FPGA (field programmable gate array) based TDCs were discussed in details. To reduce system complexity and enhance its flexibility, FPGA TDC was finally chosen as the design scheme in the TO detector readout electronics.Chapter Three presents the design of the TDC module, including the key parts, such as the method of doule edge time measurement in single channel, and CAM (content addressable memory) based trigger matching.In Chapter Four, test results of the time-to-digital conversion module were presented, including, the performance of nonlinearity, time measurement precision, as well as the trigger match function. The results indicate that 24 TDC channels were successfully integrated within one single FPGA, and a time precision of 25 ps RMS is achieved while the trigger matching block functions well, which satisfies the application requirements.This dissertation is concluded in the fifth chapter, and the plan for future work is presented.