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The Study Of Analog Circuit Evolutionary Model On Netlist-level And Evolutionary Design Platform

Posted on:2015-01-01Degree:MasterType:Thesis
Country:ChinaCandidate:M XueFull Text:PDF
GTID:2268330431950013Subject:Circuits and Systems
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Analog circuit is an indispensable part in all electronic systems who communicate with the outer world, the research on analog circuit automated design is deserved because of its great economic and research value. It is a promising research method to use evolutionary algorithm which imitates the natural evolution process for the research of analog circuit automated design. In this dissertation, the research of analog circuits evolutionary design method mainly includes two aspects:analog circuits evolutionary algorithm model and the research for analog circuits evolutionary design platform. Netlist-based circuit representation encodes circuits according to the format of circuit simulator’s input file, this circuit coding scheme describes circuits in a intuitional way and have no limit on circuit topologies. We study analog circuits evolutionary algorithm model based on netlist-based circuit representation. The circuit described by netlist-based representation is similar to the description of the graph in graph theory, so we can adopt the knowledge of graph theory to describe circuit topologies to extract eigenvalues from topologies, these eigenvalues can help us further our study on circuit. The application examples of evolution of analog circuit design in the engineering environment is few, the main reason of this is the big difference of component model used in research and industrial environment, so it is necessary to study analog circuits evolutionary design platform in industrial-grade circuit design software, we study analog circuits evolutionary design platform in Cadence DFII environment.The work and progress of this dissertation are summarized as follows:1. We propose a kind of netlist-level analog circuit evolutionary algorithm model. In this model, we use connecting point set mechanism to initialize circuits cooperating with connecting point checking mechanism to avoid invalid individuals as much as possible, then the evolutionary process is realized by different mutation operators. The experimental results show that this evolutionary algorithm model not only suits for circuits which contain two-terminal components, but also can promotes to circuits or circuit modules which contain three-terminal components or more.2. The netlist-level analog circuits evolutionary algorithm model motivate us to describe circuit topologies by graph theory, we choose four concepts to describe topologies to be the eigenvalues of circuit topologies. We adopt classification algorithm and put these eigenvalues in studying the relation between circuit topology and its fault tolerance. We use the classification hyperplane trained by logistic regression to guide the evolutionary process and this method is beneficial to improve the fault tolerance of circuit. This kind of circuit fault-tolerant design method based on machine learning is a valuable method and is worth to further study.3. We combine the SKILL programming language with the open command environment for analysis (OCEAN) in Cadence DFII environment to set up the analog circuit evolution platform successfully. SKILL is responsible for realizing evolutionary algorithm, and OCEAN is used to active circuit simulator. This platform provides a reliable research platform for the practical application of analog circuit evolutionary design.In conclusion, we study on analog circuit evolutionary design in this dissertation, we pose a kind of netlist-level analog circuits evolutionary algorithm model based on connecting point set and set up a platform of analog circuit evolutionary design in Cadence DFII environment, hoping that our work could provide some ideas and inspiration for others in the field of analog circuit evolutionary design.
Keywords/Search Tags:analog circuit, evolutionary algorithm, netlist-based circuitrepresentation, evolutionary design platform, Cadence DFII environment
PDF Full Text Request
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