Nano-electronic Circuit Reliability Design Based On Evolutionary Algorithm

Although the complementary metal-oxide semiconductor (CMOS) technologies have met the demand of increasing functionalities by scaling exponentially as Moore’s law predicted in the past four decades, the scaling is predicted to approach fundamental limits at the end of next decade. Nano-electronic technologies has recently been studied as one possible heir to CMOS technologies to continue the scaling when CMOS technologies hit their limit, some novel nano-electronic devices have been fabricated and characterized in chemistry labs.However, the nano-electronic systems fabricated by nano-electronic devices and nanotechnology are also facing great challenge. As a result of the extremely small size of nanodevices and poor control in the nanofabrication process, there exist serious parameter variations in the nano-electronic systems. Taking into account the parameter variations is one key step for reliable operation of system. Thus, some researchers propose the variation tolerant logical mapping (VTLM) technique to mitigate the parameter variations.At the meantime, the electronic systems will also be influenced by some other uncertain factors, including changes in the environment, aging and approximate models. It needs to consider negative effects brought by the uncertain factors in the system design and make the system perform its intended functions satisfactorily while operating under the specified operation environment, which can be called as system robust design.Variation tolerant logical mapping and system robust design belong to system reliability design, the difference between them is:system robust design consider the influence of uncertain factors in the process of parameter designing, while variation tolerant logical mapping is applied after the process of parameter designing, which takes use of configurability of crossbar to reduce the effects of parameter variations. This thesis mainly focuses on the study and algorithms on the two system reliability design method, the main work and innovation are summarized as follows:1. A systematic study on nanoscale crossbar and logical mapping problem is presented. The crossbar can be divided into diode based crossbar and transistor based crossbar with different delay models according to the basic elements. Two common used logic mapping model on nanoscale crossbar are described, namely the matrix mapping model and bipartite graph mapping model.2. A new memetic algorithm based on multiobjective evolutionary algorithm is proposed to deal with the variation tolerant logical mapping on nanoscale crossbar. The variation tolerant logical mapping problem is formulated as a multiobjective optimization problem, and the calculation of delays of two types of crossbar are introduced. A local search, named as greedy reassignment local search, is designed based on the useful information obtained from the variation tolerant logical mapping problem. The local search is introduced to NSGA-Ⅱ (memetic algorithm) to deal with the variation tolerant logical mapping problem. The effectiveness and efficiency of proposed methods are testified by comparing with NSGA-Ⅱ on a large set of benchmark instances of various scales.3. A hybrid multiobjective evolutionary algorithm is designed to solve the variation tolerant logical mapping on nanoscale crossbar adhering to a bilevel optimization framework. The problem is modeled as bilevel multiobjective optimization problem, which make it easier for the design of the method. The lower level optimization problem, most frequently tackled, is modeled as the Min-max-weight and Min-weight-gap Bipartite Matching (MMBM) problem, and a Hungarian-based Linear Programming (HLP) method is proposed to solve MMBM in polynomial time. The upper level optimization problem is solved by evolutionary multiobjective optimization algorithms, where a greedy re-assignment local search operator, capable of exploiting the domain knowledge and information from problem instances, is introduced to improve the efficiency of the algorithm. The numerical experiment results show the effectiveness and efficiency of proposed techniques for the variation tolerant logical mapping problem.4. A new method that combine the differential evolution with hybrid analysis method is presented to solve the worst-case circuit tolerance design problem. The hybrid analysis method is comprised of two commonly used worst-case circuit tolerance analysis approaches, vertex analysis and Monte Carlo analysis. The search direction of differential evolution is leaded by vertex analysis at the first stage, through which we can reduce the computational complexity of fitness calculation dramatically. Monte Carlo analysis, a higher accuracy analysis method, is applied to ensure the quality of the solutions at the second stage. By cooperating the two analysis methods, the proposed method can get a proper balance between accuracy and time efficiency. The experiment results show the effectiveness and efficiency of proposed techniques for the circuit tolerance design.