Research And Implementation Of Low-Power Pedestrian Detection System Based On Fpga

With the fast development of Internet of Tings and computer technology, the embedded system have got rapid development in hardware, power consumption and of software design patterns. At the same time, more real-time applications have been deployed in embedded devices and a balance of computing speed, power consumption and security need to be achieved.Real-time image-based pedestrian detection is an important implementation in many domains such as security, entertainment, monitoring and robot. The algorithm based on the Histogram of Oriented Gradient (HOG) and Support Vector Machine (SVM) is the most widely used. However, its high computational complexity makes it impossible to implement in a traditional embedded CPU in real-time.To realize an embedded real-time pedestrian detection system based on image is a challenging task. In this article, we proposed a pedestrian detection system based on field programmable logic gate array (FPGA) hardware with the most widely used algorithm of HOG and SVM. In our implementation, a binarization process is proposed to replace the standardization process. Based on this modification, all multiplication can be instead by addition operation during the classifying process of SVM classifier. In addition, the lookup table and pipeline architecture are used to reduce the computing complexity and power consumption.The initial experimental results demonstrate that the proposed implementation achieved293fps by using a low-end Xilinx Spartan-3e FPGA. The detection accuracy attained a miss rate of1.97%and false positive rate of1%. For further demonstration, a prototype is developed using an OV7670camera device. With the speed of the camera device,30fps can be achieved, which satisfies most real-time applications. Considering the energy restriction of the battery-based system at a speed of30fps, the implementation can work with a power consumption of less than353mW.In addition, according to the big difference of processing rate between each module, module reuse is adopt to improve the detection speed. The dynamic reconfiguration technology is also adopted in our system. According to the demand of detection rate and different detection target, different modules of HOG and SVM can be deployed on the FPGA at run time.