Research Of Wear Leveling Strategy For Resistive Random Access Memory

With the rapid development of Internet of Things(IOT)technology,small but powerful embedded devices are being widely deployed as nodes of the IOT,adapting to and supporting rich applications.Embedded devices are the underlying infrastructure of the IOT,which play a more and more important role.As the scale of data that these embedded devices need to perceive and process is growing,higher requirements are put for their storage systems.At present,Dynamic Random Access Memory(DRAM)is main memory of most embedded devices,but the static and dynamic power consumption of DRAM is high,which cannot meet the requirements of storage capacity and service life of IOT.The emerging non-volatile memory(NVM)has the advantages of non-volatility,high storage density,low static and dynamic power consumption and so on.The embedded device based on NVM will be able to reduce the overall power consumption of the embedded system,improve the storage capacity and solve the problems of DRAM.Among them,the performance of Resistive Random Access Memory(ReRAM)is similar to that of DRAM.It can be combined with modern CMOS technology and adopt crossbar structure to achieve the minimum storage density of 4F2,which is suitable to be used as the main memory of embedded devices.However,ReRAM has limited endurance,and write latency and the endurance of crossbar is discrepant.At the same time,embedded device need to meet the requirements of quality of service and execution time of tasks.For these reasons,the construction of embedded system based on ReRAM needs to consider the endurance of ReRAM and ensure the real-time performance of the task at the same time.In order to ensure the execution time of embedded device tasks and prolong the endurance of ReRAM,a deep reinforcement learning based on wear leveling strategy is proposed in this paper.Specifically,this paper uses HSPICE to establish the ReRAM crossbar model to obtain the write latency and endurance of memory cells in different locations in the crossbar.Secondly,according to the application-specific features of embedded applications,the access characteristics of embedded applications are obtained by offline analysis.Finally,the proposed method accepts the memory access behavior of embedded tasks and the write distribution of ReRAM as the state,map the memory request to the corresponding storage location,the mapping behavior will receive reward of punishment according to the optimization goal.If the execution time of the task is guaranteed and the write distribution are evenly,the corresponding actions are rewarded.On the contrary,if the memory access time is too long and the task execution fails or the write distribution is too intensive,the corresponding actions will be punished.After the training phase,the system can make a better address mapping according to the characteristics of the task and the wear of the ReRAM,and extend the endurance of the ReRAM as much as possible to meeting execution time of the task.We evaluate the proposed scheme through simulations with a serial of real-world tasks from Mibench and HERMIT.The evaluation results show that our model can extend the lifetime of ReRAM up to 118%compared with the baseline model while guaranteeing the execution time of all tested tasks.