Based On Vision Inspection Research Of Chip Package Platform Location Algorithm

As the basis for the industrial economy of the times, the microelectronics industry plays an extremely important strategic significance in the national economy, national defense construction and modern information society. Microelectronics industry, which includes the design, manufacture and packaging of three separate industries. Among them, with the development of the microelectronics industry, microelectronic components packaging is also becoming increasingly important.With chip packaging technology is growing high integration, high performance, multi-leads and fine pitch, wire bonding accuracy requirements are also increasing, which as one of the most commonly used chip packaging technique. Every step in the wire bonding process also involves the positioning problem, therefore, the visual system has become one of important factor affecting the chip package accuracy.This paper uses machine vision technology and digital image process technology to realize the image recognition and position system of chip packaging technology. The primary research content of this article includes:1) For chip packaging visual positioning system done more comprehensive research. According to the chip wire bonding characteristics of mass production, research and testing software runs in two modes, namely experiment mode and test mode The image feature of the chip use the method of intelligent recognition software acting in concert with artificial definition in the experiment mode to realize the quick definition of chip feature region and type and form characteristic information and algorithm configuration file corresponding with a particular type chip. The rapid positioning of solder joint and wire bonding frame is in the light of the chip features and algorithms file of the experimental mode during mass production. This approach can simplify the complexity of the algorithm and improve the efficiency of position detection as well as the quality of wire bonding in the batch operation.2) According to the characteristics of the die images, minimum enclosing rectangle fitting was used to solve each solder joints the actual location of the chip, real-time correction due to the placement and clamping position error in the chip wire bonding process. By building a list of virtual corner obtained the minimum bounding rectangle of solder joints, obtain the actual coordinates location of the solder joints, and feedback to the bond head correction system with the offset and offset angle of the actual coordinate position relative to the ideal coordinate position to achieve precise bonding, improving the accuracy of die-bonding.3) In connection with the Image features of the lead frame,by analyzing the function between the edge straight line of the lead frame pin and the circumcircle of pin joints,creating a mathematical model,in which the objective function is center position on the circumcircle of pin joints, The constraint is that the distance from the center to the two pins is equal, besides, the radius of the spot is smaller than the distance from the center to the pin.The experimental results show that he algorithm can achieve the correct position of the lead frame jointsIn summary, this paper studies the visual positioning technology for chip packaging in depth, and does experiments and verifies the presented algorithms by using die and frame lead images, and results show that the algorithms put forward by the paper gain better detection and classification effects. The research achievements of this paper for improving the level of computer vision inspection technology and promote the application of computer vision in the chip package has a certain theoretical and practical value.