Design And Research Of The Display Control Mechanisms For Multi-source

The video information plays a more and more important role in the expression of information inmultimedia technology. Since one video source such as camera sensor gets a single scene, it isdifficult to meet the demand in multimedia information. So multi-video source display technologyemerged. The high price of ASIC limits its wide used in consumer products. With multimedia SoC’srecognition by industry with its characteristic，such as flexibility, scalable, extendibility, softwareco-simulation, and so on, the multimedia SoC based on the IP core of display control unit formulti-source has become the mainstream application.In this dissertation, the IP core supports four video source alpha-blending real-time dislaying.The corresponding code is developed with Verilog HDL language. This design uses the industry’spopular AMBA interconnect, AHB bus interface standard makes it easier to be integrated indifferent chips, easy to reuse the test environment and test vectors based on the bus.According to the characteristics of multi-image blending, a power efficient self-adaptivepipeline and corresponding on-chip buffer hardware architecture is proposed. Depending on colorformat of each input image, the proposed blending engine adapts pipeline architecture and workstatus of each stage automatically to improve power efficiency.The IP’s pixel fetch module implements reading video data by four independent channels, andsupports burst transfers. In the color space conversion module, this dissertation adopt a unifiedconversion formula to achieve the four RGB and YCbCr format conversion under the standardsupports ITU-R BT.601and ITU-R BT.709,which saves hardware logic, improves the processingspeed of color space conversion by pipeline architecture. This dissertation adopts bi-controllablecircular buffer structure to achieve a smooth playback of high-quality images. To meet the needs ofa variety of video play, the dissertation uses alpha-blending and color key to achieve a transparentcolor display and filtering capabilities.In the low-power processing, the dissertation adopts bi-controllable circular buffer structure todecrease pipeline stalls, keeping pipeline smooth. What’s worse, selective-fetching pixel andself-adaptive color space conversion techniques are adopted to reduce the power consumptionfurther.The dissertation builds a test platform and its functional simulation by Synopsys’s VCS, andverification FPGA prototype in Vertex-5board. The report of functional simulation and verificationFPGA prototype demonstrates that the designed achieved the goal.