A Design Of12-bit500-kS/s Cyclic ADC Applyed For CIS

The eyes are the main tool that help human to understand the world, the image isthe form that helps eyes to get information. So the image information is veryimportant for people to know the world. With the progress of science and technology,many equipments which are used to obtain image information to replace human eyesare made. They are used in consumer electronics, industrial production, aerospace andother fields. The core of this kind of equipment is the image sensor, which is thephysical interface between the external system and an internal DSP. It could convertlight into electrical signals. The image sensor could help people understanding thecourse of events better with Superior performance.Chapter1provides an overview of CMOS image sensors.The key performanceindicators of the CMOS image sensor is dynamic range and speed, dynamic range isthe ratio(dB) of the maximum intensity which can be processed of the image with theresolution of the sensor. Speed refers to the image sensor frame rate, the number ofimages can be obtained with per second.Chapter2introduces the analog to digital converter for image sensor readingcircuit.It mainly includes three structures: single slope ADC, SAR ADC and cyclicADC. Single slope ADC architecture is simple but the system clock requirements aretoo accurate. SAR ADC does not have high requirements on the system clock chip,but it employs a large chip area. The performance of Cyclic ADC does not have highrequirements on the clock, the chip area is small, this paper chooses cyclic ADC.Chapter3introduces some basic concepts of ADC, first introduces the developmentstatus of it, and then introduces the working principles of several common ADC,finally introduces the performance parameters of the ADC.Chapter4describes the work principle of cyclic ADC, analysis of the non-idealfactors of the system, and calculates the internal modules required index.Chapter5introduces the internal module of Cyclic ADC, including operational amplifier, comparator, and introduces the design process of the module, gives thesimulation results and the circuit layout.Chapter6makes a summary of all the paper.This paper designs a12-bit500-KS/s of cyclic ADC, and uses for the readingcircuit of CMOS image sensor system. Then, the ADC layout were drawn based onGlobal Foundries0.18μm1P4M CMOS technology library.the total size of the chipis8μm×374μm. After the layout drawing, uses the Calibre tool to extract the layoutof parasitic parameters and uses the Spectre software in different process corner tomake post-simulation, the post-simulation results show SNDR greater than63.7dB,ENOB greater than10.3bit. This article cyclic ADC with high accuracy, low powerconsumption, small chip area, and can be used for high speed and large dynamicrange of CIS read circuit.