Optimal Design Of High-speed Circuit Board Based Optimize Pi Power Integrity

With the rapid development of IC technology, The Voltage value decreases on the high speed board, however, the current and power have continued to increase, all of these will cause the problems about power integrity (PI) and signal integrity (SI). We can use Optimize PI tools to optimize in the network power distribution system about design of decoupling, base on the frequency characteristic about decoupling capacitor, we can use frequency target impedance method make the value is lower than the target impedance, so as to reduce the noise of entire electrical power distribution system impedance.The high speed board is optimized considering under the condition of power integrity, mainly from the number of decoupling capacitors and the optimization placement to design. The reasonable number of decoupling capacitors can reduce design area to speed plate and also can reduce the manufacturing cost. Making optimization of the data and the initial design phase contrast after optimization, in order to get the optimal solution.When the number of decoupling capacitors meet the design requirement and at the same time manufacturing cost is reduced, then consider its position. Reasonable position can also reduce impedance. From optimized contrast, we further out the exact position of coupling capacitor in high speed board, this helps to design a more reasonable. The whole board is validated after finishing optimization, the optimization result is still less than the target impedance.This paper mainly study the optimization design of high-speed board, mainly from study of decoupling capacitors on the number and location, the manufacturing cost only consider the number and type of capacitor, so it was not full.