Analysis And Decoupling Design Of Multiple Chips Power Delivery Network

With the development of the circuit board in high-speed and high-density trend.Appearing the kind of circumstance that multiple chips share the same power/ground plane is inevitable.In this condition,the power/ground plane behaves both global and local characteristics in different frequencies.In globel manner the power port of every chip interact with each other,causing that the impedance and simultaneous switching noise of each port stack together;In local manner,the decaps provide the high speed current for IC and there is little effect among ports of each IC.Meanwhile,the size of IC is becoming 22 nm orsmaller,the voltage to supply the IC decreasing,the current drawed by the IC increasing,the power of the IC Consumption enlarging,the factors above cause power supply noise tolerance very small and lead to analysis and design today’s high-speed Power Distribution Network more and more challenging.To obtain the relatively stable voltage in IC’s power pins.It’s necessary to design a decouple network specific to multiple chips.Moreover,the decaps location and layout patterns have significant influence on the decoupling performance.For single decap,the location mainly affects the spread inductance between the IC and the decap and the shorter the distance the smaller the inductance.So it’s better when the decaps close to the IC.For multiple capacitors,the layout pattern also affects the performance.At present there are two common patterns for the capacitor’s layout:the ring pattern and the grid pattern.Through the simulation,the ring pattern is better than grid pattern whether from the impedance curve or the peak of SSN noise under the same condition.This paper analyzes the equivalent circuit model of each component of PDN and their impact on PDN and the design methods of multiple chips.Through comparing the difference of multiple input impedance and single input impedance in characterizing the Power Distribution Network,it illustrates that the multiple input impedance is more appropriate than single input impedance.Baseed on this,we utilize the multiple input impedance of each power port of the IC to guide the multiple chips PDN designing.Firstly,through SI-wave software to extract the multi-input impedance and using vector fitting tool to transform the carve into rational function. Then imported the function to a capacitor selection software,to obtain the decoupling scheme and put the capacitor to the IC in a reasonable way.According to the same method,choose the capacitor for other port until the impedance of every IC below the target impedance.finally,time domain simulation shows the validity of method proposed by this paper.