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Study On Optimazation And Simulation Of System Scheduling In Semiconductor Final Testing

Posted on:2015-03-09Degree:MasterType:Thesis
Country:ChinaCandidate:Z L BaiFull Text:PDF
GTID:2268330428475952Subject:Management Science and Engineering
Abstract/Summary:PDF Full Text Request
Semiconductor manufacturing is complex, capital-intensive and costly featured with sequential processing and batch processing, especially the reentry.The main feature, the phenomenon of reentry appears multiple times in the semiconductor manufacturing process. As one of the most important high-tech industries, nowadays the semiconductor manufacturing is confronted with many opportunities and challenges simultaneously. The rapid growth of the semiconductor industry brings greater economic benefits. Mean-while, the fierce competition urges the semiconductor company to increase the productivity and utilize resources effectively. Therefore, this issue has been highly concerned by scholars and insiders.Semiconductor manufacturing system is formed by the front and the end process. The front process has been researched very well by scholars, because that required much more steps and particularly expensive equipment. However, this situation has been immensely studied and reasonably optimized by scholars, accordingly the vulnerability of end processing should be highlighted. As an inseparable part of chip fabrication, the performance of the entire production system is mainly subject to end test. With Extendsim as the platform, this Paper studies job scheduling, commissioning strategy and system balance of semiconductor terminal test system to explore scheduling optimization strategies.In this Paper, heuristic scheduling rules and four-lever scheduling policy (FSP) are applied to optimize the chip test system, specifically, firstly using the most optimized batching method in the grouping of simulation system parts, secondly, providing teaming job to feeding avoid that parts in different categories are in the line of batches, to increase the time for system preparation and the waiting time of parts in the buffer area, thirdly, for sophisticating sorting of parts in the buffer area of test center, combining heuristic algorithm, VNS and heuristic scheduling rules to schedule, lastly adopting heuristic scheduling rules to schedule against the burn-in oven reentrant center. In terms of system balance, a favorable result is concluded based on RSALB, FSP and order simulation analysis on different loads with ExtendSim.
Keywords/Search Tags:Semiconductor terminal test, reentry scheduling, system load balancing, ExtendSim Simulation
PDF Full Text Request
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