The Research And Optimization Of Video Coding Based On The Universal Dual-core DSP

With the embedded system performance and image compress technology continues to improve, how to achieve high efficiency video encoder in embedded platform has been a research hotspot. While the present video encoder research based on embedded platform is achieved mainly through the embedded DSP (digital signal processor) platform. The characteristics of DSP are that computing capability is better and speed of operation is very fast, with the wide applications of streaming media and the improve of video encoding complexity, the existing single-core DSP platform is difficult to satisfy the characteristics of video encoding that the amount of data transfer is very large and parallelism is very high, and multi-core processors provide a powerful platform for video coding data processing.According to the universal dual-core DSP processor MPC8641D memory structure and the characteristics of Cache, this paper studies and analysis all kinds of basic frame structure to realize the high efficiency video encoder, design a dual-core DSP processor to suit the video encoder, to improve the work efficiency of video coding procedure in DSP platform. At the same time, in order to more fully utilize DSP resources, to ensure the quality of image compression, select the most suitable encoder rate control parameters for this paper.In addition, in order to make more efficient use of DSP resources to achieve high efficient video encoder, this paper studies and analyses several classic Cache replacement algorithms for L2shared cache replacement algorithm of dual-core DSP platforms, such as LRU, MRU, RAND, puts forward LRU2-MRU hybrid Cache replacement algorithm to suit video encoder in dual-core DSP platform, the algorithm improves the Cache hit ratio and the use efficiency of the video encoder program data.Freescale Company produces the embedded processor MPC8641D is a high performance PowerPC dual-core processors, it has the relatively high signal processing ability, and has128-bit vector processing engine and dual memory controller, it also can visit memory by low latency, high bandwidth access, so it proposes the conditions for achieving the highly efficient video encoder. Between the two PowerPC e600cores of MPC8641D exchange informance through high-speed internal bus.Firstly, this paper simulates universal dual-core DSP based on embedded MPC8641D processor in Simics simulator, and verifies the efficiency of the proposed LRU2-MRU algorithm by three groups of experimental results. Secondly, the video code is transplanted into the dual-core processor architecture, and through the four group experimental results verifies that the video encoder encoding has the optimal efficiency, when the Cache replacement algorithm is the LRU2-MRU algorithm. Finally, this paper simulates the signal to noise ratio and quantitative parameters of the video encode by four groups of quantified parameters, validates the influence of quantified parameters for the video encoder. In this paper, the research and implementation of the video encoder based on the universal dual-core DSP platform compares with the LRU-MRU algorithm, the encoding time of I frame reduces by an average of4.95%, the encoding time of P frame reduces by an average of15.32%, and the motion estimation time of P frame reduces by an average of21.4%. Compared with the LRU algorithm the encoding time of I frame reduces by an average of21.47%., the encoding time of P frame reduces by an average of21.47%, and the motion estimation time of P frame increases by an average of25.49%. Experiments show that the improved video encoder can effectively enhance the coding speed and the picture quality.