Design And VLSI Implementation Of Unified Architecture For Computation Of Discrete Orthogonal Transform

Discrete orthogonal transforms (DOT) has a very important position andmany applications in information processing, especially in video, imageprocessing, and its algorithm and its hardware implementation have been a hotresearch field of information processing. After the new video compressionstandard H.265-HEVC published, single kind of DOT has been unable to meetthe application requirements, multi-kind DOT unified architecture will becomehot research field. To meet people’s increasing demands in video and imageprocessing, developing the unified architecture for a variety of orthogonaltransform is a serious problem.For the above hot research problems, the research focus on DOT algorithmsand three kinds of DOT unified architectures. The main contents include:1. Firstly, an algorithm based on2n-poins DCT is proposed. By the nature ofparity decomposition and trigonometric, the input signal regularity of thealgorithm and transformation function of algorithms are achieved. Then DST,IDCT, IDST, DWHT and Haar_DWT algorithm are depicted based on DCTalgorithm and algorithm model adapt to unified architecture is achieved. Thismodel becomes theory base for the following VLSI unified architecture design.2. Secondly, taking full advantage of the nature of trigonometric functions todeduce intrinsic relationship between several discrete orthogonal transformations,and designed several typical unified architecture, includes DCT-DST unifiedarchitecture, DCT-DST-IDCT-IDCT unified architecture and Haar_DWT-DWHT-DCT unified architecture. Based on these architectures, modularity andsimulation are realized, synthesised by Synopsys Design Compiler tools, andmade comparison between area, power and speed. At last, layout is realized byCadence Soc Encounter. The experiment shows proposed unified architecture has simple calculation and low hardware consumption, and eays to realize VLSI.3. Finally, performance of unified architecture in practical application isresearched. Calculate accuracy and recovery feature of unified architecture areverified. And verification platform is designed according to accuracy andrecovery verification requirement. The platform is developed based on FPGAdevelopment board. The result indicates that proposed unified architectures arehigh calculation precision and good reducibility.