VLSI architectures for adaptive image compression using discrete wavelet transform

Digital image compression has recently attracted considerable interest due to its critical role in emerging imaging applications such as video teleconferencing, High Definition Television (HDTV), and interactive visualization, etc. The Discrete Wavelet Transform (DWT) has been shown to be an efficient tool for eliminating the redundancy in image data. Image compression using DWT results in good compression ratio while maintaining acceptable image quality. However, the throughput of DWT-based image compression is not adequate when implemented in software on a general purpose computing system. The performance of a software implementation cannot meet the requirement of many real time applications. To take advantage of the current VLSI technology, hardware support for image compression techniques and special purpose custom VLSI chips are fast becoming standard components for image processing systems.; In this dissertation, we develop a new systolic architecture which works for both image decomposition (DWT) and reconstruction (Inverse DWT). This new architecture produces one output per clock cycle (100% utilization of the hardware) and can be easily implemented using current VLSI technology. A basic circuit block for this proposed architecture is designed and simulated. Based on the simulation results, the overall system results in much faster throughput than is possible with a software implementation on a general purpose computer. Two adaptive image compression systems are also proposed. Exploiting this new systolic VLSI architecture for DWT, these two pipelined systems are very efficient and suitable for VLSI implementation.; The design of these image coding systems is based on pipelined modules. We have developed the primary modules such as DWT, Spectral classification, Bit Rate Allocation and Embedded Zerotree Wavelet (EZW) modules. Pipelining these well designed modules leads to high performance adaptive image coding systems.