Research Of FPGA Routing Technology

FPGA (Field Programmable Gate Array), as ASIC field emergence of a semi-custom circuits with low design cost, time to market fast, flexible and easy to modify design, long life-cycle, etc., it is one of the most common applications in the digital circuit design. Today FPGA design flow mainly includes two aspects:the first step is the layout, the task is to assign the sub-circuit technology mapping module which was divided into specific programmable IP core logic cells; the second step is wiring, which is to give these place a good logical unit to connect.Although many CAD tools on market can complete FPGA layout, global routing, global and detailed routing, there are differences of tools to achieve them.Most of these layout tools are implemented and improved based on the VPack algorithm, simulated annealing algorithm, A*algorithm,Dijkstra algorithm,maze routing algorithm and path search algorithm.In order to meet the substantial increase in the quantity and quality of FPGA,it is a very importment significance to improve FPGA placement and routing tool actively.To FPGA, this paper makes the following presentation:the significance,domestic and international status of FPGA; the basic structure of FPGA; the packaging technology of FPGA; the layout techniques of FPGA and the routing technology of FPGA.In this paper, the research tool will be run under Linux. Install Cygwin under Windows, using Xwin-Sever, install and operate VPR in this virtual platform. VPR not only can achieve the FPGA placement and routing requirements, it is also the wiring tool which need the minimum sum of process in current FPGA routing tool. Even so, it still has much room for improvement. In this paper I have complete the following three improvements:First, VPack original algorithm is studied and improved, after adding two key factors eliminated to the key section of attracting a function of BLE in VPack, the average speed cabling increased by0.04746%.Second, the VPR in routing-driven routing is studied and improved:(1) using a linear model Elmore alternative model to optimize the delay;(2) the original wiring fixed cost base to a dynamic basic cost function functions. After the improvement I find that the improved timing-driven router latency decreased by nearly3.67%, while the CPU time was reduced by25%. Third, the path search algorithm is studied and improved:Modify the valuation function, ignoring the search for unnecessary paths, has been greatly improved for large short-circuit, its search speed is probably increased by about0.048%, the delay reduces by0.008%.Through this experiment, it is a foundation for the follow-up improvement of the FPGA placement and routing tool.