Research On Multi-Project Wafer Floorplanning And Dicing Algorithms

As integrated circuit (IC) technologies develop these years, especially since IC feature scale goes further into nanometer scale, IC manufactory cost skyrockets. Aiming to reducing prototype fabrication costs, both academia and industry use multi-project wafer (MPW) technologies widely. In a MPW project, different IC designs from different design organizations can be packaged into same mask, and these IC designs are fabricated at the same time. IC design organizations share mask and wafer costs according to their IC designs’area, and obtain enough chips at prototype design stage.To address yield loss from random defects, a new MPW floorplanning algorithm is proposed in this thesis. This proposed algorithm can increase production margin to compensate fabrication loss caused by defects through introducing defect models. Simulated annealing algorithm is also modified to quantify MPW floorplanning constraints. The proposed algorithm can traverse whole solution space at high temperature, and thus escape local optimal solution traps, and also can find solutions that satisfy constraints at lower temperature.MPW dicing problem is divided into two sub-problems, pre-dicing and post-dicing, according to procedure executing time point and purpose in this thesis. Mathematic model and algorithm for post-dicing problem are constructed. Chips’ status information is introduced into dicing algorithm, to avoid cases that bad dies are diced at the expense of destroying good dies,and also to maximize whole interest.