The Analysis And Design Of Rail-to-Rail Auto-Zero Operational Amplifier

Although the digital signal processing algorithms is becoming increasingly more powerful in modern integrated circuit (IC) currently, the analog circuits have proved fundamentally necessary in the systems which deal with the natural signals. On the other hand, with the decrease of the chip’s size, the lower supply voltage and the request of exactly control which are great challenges to the design of analog circuits. As the fundamental part of the analog circuits, the operational amplifier (OP-AMP) also faces this difficulty in design progress. So, a rail-to-rail auto-zero OP-AMP is designed to detect the tiny input signals in exactly control industry, and to expand the common-mode input range and the output swing.This design consists of two parts:The one is a rail-to-rail input module which use charge balanced sampled data techniques to convert a differential input voltage into a single ended signal, discarding the traditional input structure that consists of a P-channel pair and an N-channel pair. The second part is an independent auto-zero amplifier which use auto-zero techniques to decrease the offset voltage that generated during the design or productive process. It is worth noticing that we add a phase and an subsidiary AMP between the auto-zero phase and output phase in the normal auto-zero techniques to further remove the peak offset voltage or the average value.With the software of Cadence Spectre, all circuits are designed and simulated based on the CSMC0.6um CMOS technology. Both the common-mode input range and the output swing are rail-to-rail, and the sample rate for differential input is3KHZ. The average input offset voltage and peaky offset voltage under the different temperatures and process corners are below lOuV and100uV. The typical power supply rejection ratio (PSRR) is about120dB, and the common mode rejection ratio (CMRR) is above125dB. The OP-AMP also features a2MHZ gain bandwidth while providing a open-loop gain of typically much greater than100dB, a phase margin of about60°. This design also has an enhanced output slew rate of4.4V/us, and its setting time is600ns. The amplifier can be used in single supply application which range from2.7V to5V, while its typical supply current is900uA when added a3V supply voltage in room temperature. The results show that this amplifier can implement its function, basically meet the expected design target.