The Analysis And Design Of Low_power Reconfigurable Cache In Embeded System

The rapid development of electronic technology greatly improves the integration degree and speed of processor, although the performance is improved greatly, the power consumption of a processor increases rapidly. The increasing of power consumption raises the chip’s temperature and reduces the chip’s stability, and also it shortens the chip life and increases the difficulty of chip design. As an important part of a processor, Cache becomes the main source of power consumption of a processor chip as its large capacity,fast speed and frequent access. Therefore the design of lowpower Cache structure can effectively reduce the overall power consumption of a processor, it is of great significance to improve the performance of embedded system.Based on the embedded system environment, we proposed two kinds of improved adaptive reconfigurable Cache algorithms.(1)By considering the capacity and the associative’s effect on the performance of Cache, a reduced-rank reconfigurable Cache algorithm is proposed, which can reduce dimensionality and reconfigure cache in view of the impact of capacity and associated performance. Taking the capacity and associated performance impact on the basis of Cache into consideration, first, determine of the optimal capacity, and then determine the search order of the optimal associativity. Second, configure cathe’s parameter in accordance with the order.search results will be judged. If the search result is poor, then continue to determine the optimal solution of association and determine the optimal solution of capacity. If the program is still in an unstable state,then adjust the threshold and searching for the optimal Cache structure to the direction of reduced missrate. The experimental results show that this algorithm can effectively reduce missrate and reduce the loss of Cache energy.(2)Based on the reduced-rank reconfiguration algorithm, a reconfigurable Cache algorithm based on instruction_working_set is proposed, since instruction_working_set can accurately reflect the internal characteristics of the program, the frequent instruction_working_set and the corresponding optimal Cache configuration parameters are recorded. When the program changes, we can reconstruct the Cache by comparing program instruction_working_set quickly and matching the eigenvalue. If the program is still unstable, we can adjust the Cache capacity and associativity from the current state by reduced_rank reconfiguration. Compared with the first algorithm, the algorithm effectively improves accuracy of monitoring the change of program and optimization of reconstruction path, we can gradually reduce missrate by adjusting the Cache capacity and associativity to stabilize the program and this method can effectively reduce the energy consumption of the system.All of the results in this paper are simulated on SimPanalyzer platform, The experimental results are consistent with theoretical expressions deduction. Comparing to latest works, the proposed designs are more creative and practical. Low power reconfiguration algorithms of this paper provide technical support for the production of low power products in embeded system.