Font Size: a A A

The Design Of High-speed Network Flow Acquisition System Based On FPGA

Posted on:2014-05-08Degree:MasterType:Thesis
Country:ChinaCandidate:M WangFull Text:PDF
GTID:2268330425480927Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Network flow acquisition is the basis of the network research. We can getinformation of the network such as the running condition, security situation, loadcondition and user’s behavior model through the network packet capture and analysis.With the rapid development of network technology, the network bandwidth has beengrowing faster than the growth of the processor performance. The traditional networkflow acquisition system consume huge resources in data capture, transmission,system copy and interrupt processing and so on, it can not satisfy the current rapiddevelopment requirements of network technology. High-speed network flowacquisitionr faced with the pressure of massive data processing.In this paper, we deeply analysis the performance bottleneck of traditionalnetwork flow acquisition technology, and the way to optimize the network dataacquisition and processing by hardware acceleration technology and data zero copy.The researching work refers the following points:1. We design a network flow acquisition system towards double10Gbps withgeneral PC platform. Based on the bottleneck analysis of the traditional network flowcollection system, we design of high-speed underlying data transmission channel,improving performance at various aspects of data transmission. We have proposedadaptive high-capacity buffer allocation, polling algorithm for packet capture andsynchronization algorithms, memory dual-mapping technology, etc. Hardwareacceleration on network traffic collection, transmission and processing, reduceprocessor load in the traffic collection, transmission and analysis. Compared with theexisting traffic system, the network data acquisition system which designed in thispaper has obvious improvement.2. According to the characteristics of the multi-core processor architecture, wedesign the network data preprocessing hardware platform responsible for networkdata capture and distribution, the platform implement the network packet capture, filtering, classified transmission and other functions, which is the key to enhance theperformance of network flow acquisition.3. Studying the classify technology for the data package which come from thehigh network. In this thesis, we design a data packet classification engine whichadopt TCAM(Ternary Content Addressable Memory) to classify packet directly. Theengine use the algorithm to segment date in a direct way and delete the redundantpart of the classification rule so that it can improve resource utilization and powerconsumption of the TCAM.
Keywords/Search Tags:network data acquisition, hardware acceleration, ring buffer, parallelprocessing
PDF Full Text Request
Related items