Design Of Interpolation Type Time-to-digital Converter

In the past decades, integrated circuit manufacturing technologies have madetremendous achievement. With the decrease of CMOS feature size, the thickness ofthe device and the channel length of the oxide layer, the system supply voltage shoulddecrease proportionally. Meanwhile, the continuous scaling of the CMOS feature sizealso results in the higher channel dope and reduces the effective control of the gate ofthe current, it will have an adversely affect on the circuit reliability. In addition, thescaling of interconnection widths and spacings caused by transistor scaling leads toincreasing resistance and mutual capacitance values. The increasing resistance valuescause voltage drop and the mutual capacitance values result in more cross-talk, whileboth factors lead to larger signal propagation delays, which have a certain extentnegative effects on the system reliability and signal integrity. To overcome thedilemma, a Time-Mode Signal Processing (TMSP) circuits are investigated in thispaper. Among the circuits, the Time-to-Digital converter (TDC) acts as a key moduleof time mode signal processing circuit, determines the merits of its performance to acertain extent.This paper mainly researches on time to digital converter. Firstly, the timeInterpolation type TDC is proposed on the basis of the traditional Vernier delay Flashtype TDC in order to obtain high resolution TDC. Its principle is similar to theVoltage-Mode interpolation type ADC. Both of them use the pre-amplifier module toreduce the quantization step, leading to high resolution. Compared to the traditionalVernier delay Flash type TDC, this structure can improve the resolutionexponentially.As an important module of the time Interpolation type TDC, its performancesdirectly depend on the time difference amplifier. The certain delay appears betweeninput and output signals in the conventional difference amplifier, which increases theconversion time of the time Interpolation type TDC. So a novel time differenceamplifier is proposed in the paper. The new time difference amplifier achieves theamplification time difference by comparing charging time of two capacitors. Since thetime difference between the input and output share a reference signal, the newdifference amplifier can effectively avoid the delay defect.Although the time Interpolation type TDC obtains a higher resolution, the complexity of the circuit increases. Hence a phase Interpolation type TDC which has asimple structure is proposed. In order to reduce the quantization step, it utilizes thephase interpolators to evenly insert the new oscillation signals into the oscillatoroutput signals, thereby improves the resolution. This new structure is quite simple andachieves less power consumption compared to the time Interpolation type TDC.Finally, the oscillator and the phase interpolator are designed and its detailedanalyses of the operating principle are given respectively. Meanwhile， HSPICEsimulations of the corresponding circuits are made and the experimental results showthe feasibility of the circuit.