Hardware Structure Design Of DFT Based On First-order Moments

The Discrete Fourier Transform (DFT) is the cornerstone of Digital SignalProcessing. It plays an important role in Digital Signal Processing. Due to the highcomplexity of computing, it is hard to satisfy the requirements of real-time processing.Now lots of more useful algorithms have been proposed to solve this problem, one of thefamous options is Fast Fourier Transform. These years, Professor Janguo Liu has inventeda method to compute DFT based on First-order moments algorithm. This solution avoidsall of the multiplications, which theoretically improves the calculation speed.Since FPGA is one of the most important components to build Digital SignalProcessing System, a hardware design based on First-order moments to calculate DFT hasbeen implemented on FPGA in this paper. According to the principle of top-down design,Control Logic, ROM, RAM, Compute Logic and Result Buffer have been well describedand improved. And a well-designed hardware structure based on pipelining to compute theFirst-order moments has been proposed. The design was written by Verilog and compiledby QUARTUSII. MODELSIM and MATLAB are used for simulation. The logic functionof the design is verified by function simulation. The result of the simulation shows that thedesign presented in the thesis not only meets design requirements but also has rationalstructure. Although there are still some problems such as high resource consumption, webelieve that through subsequent improvements the design will have a great prospect.