Verification Of H.264Decoder On FPGA

Most of the video devices have adopted H.264compression standard. For thetechnology of entropy encoding, DCT transformation and intra/inter prediction,compression rate has been greatly improved. With the design complexity increasingin H.264decoder, higher verification complexity is also demanded. Therefore,demands for chip verification has been challenging the traditional methods.This paper compares several methods and strategies in verificationmethodology for H.264decoder verification. We would complete the functionverification based on the verification points extracted from each sub module indecoder. With the output results and simulation compared to the golden model, thefunction of each sub module can be proved.After the function verification, we would build a SoC platform in which H.264decoder is integrated as custom IP. In order to solve the conflict between data accessspeed and decoding speed, an efficient memory data organization would beestablished. By the RTL simulation, we can make sure the function stability ofSoC. At last, we would finish the verification based on FPGA by generating bitstream after synthesizing, translating, P&R process.Verification results show that the H.264decoder can meet the demands ofdesign specification and realize the real time decoding process of HD video.