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Research Of Structural Fault Behavior Based On Co-simulation

Posted on:2014-11-20Degree:MasterType:Thesis
Country:ChinaCandidate:D D ZhengFull Text:PDF
GTID:2268330422950621Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
With the explosive development of the computer, the computer system is widelyused in aviation, finance, transportation, telecommunications, health care, education andother industries that connect to people’s life, and has become the essential infrastructureamong these industries to maintain and manage information. It makes the developmentand application of fault-tolerant computing becoming more extensive and in-depth, thusobserving the reliability of computing is significant and become a hot research field.However, following Moore’s Law the development of the computer grows so fast withincreasing density of integrated circuit, which means factors such as the temperature ofthe thermal effects, current consumption will probably greatly increase, so that thecircuit is triggered transient faults, intermittent or permanent failure probability offailure also increased significantly. To do this, carry out the processor hardware failurehierarchical software fault-tolerant technology research is necessary.In this paper, we focuses on the fault behavior characteristic of processor hardwarearchitecture level, the core work is to complete a joint simulation-based capture systemwhich can find out all abnormal events. We start the study with analysising RieslingArchitecture Simulator and RTL Simulator. The first part of the work is to analyze thesystem components, internal functional units, simulator lines and so on. Besides, wedesign the communication mechanism interface between the simulator and the emulator,play an important role in the abnormal events capture system.The most important research work is to design the abnormal events capture system,which is composed of three major exception capture modules. The TLB exceptioncatching module main job is to capture all TLB-related exceptions, and let TLB insimulator and TLB in emulator be consistent. Interrupt exception capture module worksfor different branches of trap catching operation. The memory exception module designappropriate capture unit for instruction prefetch and read-write operations, and maintainstorage synchronization. Thus the abnormal events capture system can automaticallycatch exception events which is inconsistent with golden reference model once themoment the co-simlation has a fault injection.The final task is to fulfil co-simulation fault injection experiment and collect theabnormal events, analyze a large number of experimental data. Then get largeinformation of fault behavior in the structure level and distribution of symptoms. Usingfault symptom information as BP neural network input classification feature informationfor fault diagnosis.
Keywords/Search Tags:co-simulation, RAS simulator, RTL, fault injection, exception trap
PDF Full Text Request
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