Design And Implementation Of The Verification Platform For NP Coprocessors

The architecture of the Internet has witnessed great changes with the fastdevelopment of network technologies, and many updates have been implementedfrequently on network devices. How to make fast deployment of network devices suchas network processors (NP) which can accommodate the development pace of theInternet has been a hotspot of researches on network. However, NP has sophisticatedstructures and is hard to verify its internal coprocessors, which brings obstacles to theinnovation procedure of NP. In this thesis we designed a Verification Platform for NPCoprocessors based on NetMagic. The main work and innovations include:Firstly, on the base of the former researches on NP coprocessors and NetMagicrelated technologies, we propose a novel architecture used for NP coprocessordevelopment and verification platform. This architecture is constructed by NetMagicplatform and adopts a design ideology characterized by the concept of hardwareblocking and software laying, software and hardware could interact with each otherthrough control stream and data stream, which improves the cooperation efficiency ofNCVP dramatically.Secondly，a novel hardware design method of the NCVP is submitted. A blockingideology is adopted to provide sub-module design and description ability of theverification platform with integrated MagicFPGA chips inside NetMagic, andenhancing the generality and flexibility of the verification platform by providing generalinterface sand test bed which can be leveraged to develop coprocessors and offeringexternal user management interfaces.Thirdly, a novel development method of control software in the NCVP is presented，the control software of the platform can be divided into three layers: the libraryfunction in bottom layer, the application-supporting function in middle layer and theapplication in up layer. By doing this, software development logic can be simplifiedwith the efficiency of software development improved.Finally, the MD5coprocessor functionality and performance is implemented andverified on the NCVP with pipeline and non-pipeline scheme. The result shows thatpipeline scheme has better performance and better suits for NP integration. The verifiedMD5coprocessor module can be directly integrated into the general-purpose andMulti-core based NP and works correctly, which proves that the verification platformcan satisfy the design requirement in terms of functionality and performance.In conclusion, the NCVP designed by this paper can satisfy the design requirement interms of functionality and performance. The achievement of this thesis has guidingsignificance and practical value to develop network processors.