| In order to acquire the camera output video image and realize real-time data processing,a project is proposed by using FPGA’s strong parallel processing ability and SDRAM’s largememory capacity. The project contains CCD camera, FPGA, SDRAM and video codec chip.Video codec chip is comprised of encoding chip ADV7123and decoding chip ADV7403.The whole project composes two control parts: one is upper computer control part and theother is lower computer and hardware control part.Upper computer control part completes the initialization of the VGA display mode andsends particular command to FPGA to start to sample a frame data. Afterwards, the data willbe uploaded to upper control part and be stored into text file. Subsequently, users can callimage prcessing interface to do corresponding processing, including threshold processing,edge detection processing and morphology processing.Based on the initial command, lower computer and hardware control part completes thespecific initialization of the acquisition and processing system. According to the steps ofvideo signal processing, six modules are implemented, including the I2C controller, decoderof ITU-R BT.656, video signal processor, SDRAM controller, VGA display controllermodule and UART controller module. These modules accomplish video decoder chip’sconfiguration, parsing, processing, storage, display and uploading. Among those modules,the processing module uses Sobel edge detection operator and Prewitt edge inspectionoperator.As a result, hardware and software validation results show that upper computer controlpart can revise FPGA’s data preprocessing mode in real time, and realize the correspondingVGA display, which includes color display, gray display and edge detection display.Simultaneously upper part can receive a frame data from lower computer part and realize thethreshold processing, edge detection processing and morphology processing.Verificationresults well in accord with the design requirements. |
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