Today, IT industry crackles with the dynamics of change and develops veryquickly. Big data and large storage will become the mainstream of data communicationin the future, creating a fast, large-capacity data transmission channel becomes the keyof the electronic system. The integration technology and interconnection technologydevelop rapidly in recent years, new serial technology, chip technologies are emerging,which provides a premise for the realization of high-speed circuit and reliableinterconnection to meet the high-speed data transmission. For constant pursuit ofhigh-speed, lots of signal integrity problems are unavoidable when high-speed signal ispropagated on the circuit board. So how to deal with these high-speed interconnectsignal integrity problems, is a major challenge for designers today during thehigh-speed circuit interconnect design, and is also the major dilemma encountered bythe high-speed circuit design.This project researched the characteristics of the PXIe high-speed backplane, andits signal integrity problems. This article begins with an overview of the high-speedcircuit theory and signal integrity knowledge, then introduced common signal integrityproblems in high-speed circuit design, and analyzed their formation mechanism. Afterthat we described the design and simulation of high-speed PXIe backplane, and havedone a detailed analysis of the simulation results.The focus of this article is the design and simulation of high-speed PXIebackplane. Signal integrity problems in high-speed circuit were discussed. In thedesign section, we used the Cadence which is the industry-leading EDA tools to makeschematic drawing and PCB layout. The simulation part we made use of the industryadvanced series of Ansoft simulation tools, at the same timeļ¼Simulation results andanalysis are given. Through the principle of the backplane design, simulation andanalysis results, this paper summarizes the high-speed backplane signal integrityproblems encountered in the design process and solutions or measures. |