Research On Anti-crosstalk Design Of High-speed Interconnect In Silicon Interposer

Currently,chip systems are increasingly demanding on interconnect bandwidth,and interconnect bandwidth has become a bottleneck of system performance.Interconnects based on silicon interposer can greatly improve the bandwidth between chips,but signal integrity issues in high-speed interconnects are also becoming more and more serious.This paper studies the signal integrity of high-speed interconnects in silicon interposers,and mainly accomplishes the following work.First of all,in order to reduce the crosstalk noise in the interconnect,a crossover-based differential interconnect structure is proposed,which can effectively suppress the crosstalk in the transmission channel.Secondly,in order to improve the anti-crosstalk performance of crossover design,four design method are proposed.By optimizing the number of crossings,the location of cross-points,the cross sectional area and coupling degree,the anti-crosstalk performance is further improved.Finally,in order to validate the anti-crosstalk design method proposed in this paper,the simulation platform is built by electromagnetic field simulation tools.For the interconnect in silicon interposer with a length of 3mm,the crossover design method proposed in this paper is adopted.Compared with the ordinary differential line,the FEXT of crossover design can be reduced by 31.8dB and 15.0dB,at 10 GHz and 20 GHz respectively.After optimizing the number of crossovers and crossover locations,FEXT can be further reduced by 10.0 dB and 9.4 dB,respectively,at 10 GHz and 20 GHz.In order to study the performance of interconnection structure proposed in this paper,worked together with transceiver circuit,the CTLE model in transceivers is built,based on cross-innterconnect channel characteristics.Combined with the DFE,CTLE is used to equalize the channel to compensate loss,and eliminate of ISI in the interconnect.The time domain simulation results show that,the proposed cross-interconnect design performs more significant crosstalk suppression.As the data rate is 20 Gbps and Voltage swing of Rx is 0.33 V,the height of eye diagram in cross design is 0.301 V,which is 0.149 V and 0.072 V higher than the single-ended and ordinary differential lines;and the width of eye diagram in cross design is 46.75 ps,which is 10 ps and 4.7ps wider than e single-ended and ordinary differential lines,respectively.The results of frequency domain and time domain simulation show that,the proposed crosstalk anti-crosstalk design method can improve high-speed interconnect performance and is expected to be applied to high-speed design in silicon interposer.