Broadband Radar Signals Digital Intercepting Method With FPGA Implementation

The rapid development of modern science makes information technology on thebattlefield has undergone enormous changes in the area of information which is the coreof modern warfare, electronic warfare systems has become an important part of thebattlefield equipment. During the world war II, headed by radar, electronic warfareequipment has played a huge role on the battlefield, by the end of world war II Germanfirst study of missile technology became a good model which incorporated informationinto conventional weapons. Nearly seventy years after the end of world war II,researchers have done a lot of work on how to fight against radar, missile and othermodern weapons, and electronic reconnaissance as one of the necessary steps oninformation against has made considerable development. This thesis carried on someresearch on missile radar detection technology, achieved traditional detectiontechnology, at the same time, studied a kind of direction finding algorithm on the fastmoving target missile. The main content of this thesis are:1. Introduce system structure of the wideband digital receiver, the system containthree sub-system which are high speed data acquisition, data rate conversion, parameterestimation. First give the introduction of the overall system structure and workingprocess, the implementation block diagram, the indicators requirements of corecomponents and the scheme of data interface; then give the architecture design of datatransformation solution; at last, describe control and parameter estimation system’s mainfunction and work flow.2. Research the algorithm of defuzzification on radar signal rotationinterferometer direction finding, which solved the fuzzy of single baseline. Comparedwith other structure, that algorithm used less reception channel with lower power andcould be easily applied in passive radar seeker. First analysis the basic principle ofdirection finding, then give the principle of the defuzzification algorithm and it has beenverified by the actual that the plan is really practical.3. In view of the receiver system indicators, digital channelized structure witheight parallel channels is adopted. Give the principle and architecture of the receiver, parallel structure of polyphase filter, parallel structure of FFT which used IP CORE andradix-2butterfly computing unit and its coefficient rules of update and arrangement, atlast software simulation for a complete set of solutions is given which includes Matlaband FPGA.4. Introduce the hardware circuit design of the system including system hardwarearchitecture diagram, in view of the function of every sub-module, the performanceindicators of core chips like ADC and FPGA are discussed, then considered the Powerconsumption of every sub-module, the system power supply plan is given, and at last,offer the resource usage of FPGA which is generated by the development software andtest the whole system.