RTL Functional Verification For Control Endpoint Of USB3.0Device Controller IP Core

The USB3.0will gradually replace the USB2.0and become the most commonUSB interface, just as the USB2.0has ever replaced the USB1.1. The huge marketprospect of USB3.0attracts lots of enterprises and research institutions to developrelated products at home and abroad. At present, the USB3.0technology hasbecome popular in foreign countries, but it is still not mature in China. USB3.0core technology products that have really independent intellectual property rightsare rare, although many domestic enterprises have actively developed relatedproducts.Under the support of the project “USB3.0device controller IP/USB3.0universal device controller/USB3.0U disk controller”, we aim to finish the RTLfunctional verification for the control endpoint of a self-designed USB3.0devicecontroller IP core. We make a deep research on the related theory of functionalverification and USB3.0specification. The main contents and contributions are asfollows:1. We first analyze and summarize three kind of verification approaches(i.e.black-box, white-box and grey-box) and tree main functional verificationtechnologies(i.e. simulation technology, static technology and formal technology).Then we choose grey-box verification approach and software simulation technologyaccording to the actual situation of the project.2. We summarize the USB3.0specification which includes architecture, basicunit of transmission, transfer types, endpoints as well as PHY interface, and graspthe design specification from the overall and the details.3. In this paper, we apply the verification theory and USB3.0specification tothe RTL functional verification for control endpoint of USB3.0device controller IPcore. Firstly, we optimize the process of software simulation technology, underconsidering the actual situation of the project. Then we do the RTL functionalverification for control endpoint of the IP core based on the process and the USB3.0specification. We propose a way to build testbench as well as a completeverification process, and focus on the design of testbench, and complete the RTLfunctional verification for control endpoint of the IP core in setup stage, data stageas well as status stage in control transfer. The testbench adopts the standard USB3.0PIPE interface as well as the modularized verification component, andseparates the mechanism of stimulus generation from the verification architecture,and realizes the automatic check about verification results. So the testbench’sreusability, scalability and reliability has been improved. The verification coversthe function of control endpoint in three aspects(i.e. standard device requests,packets and retransmission mechanism) and realizes the complete coverage aboutall of the function points for control endpoint, and brings the code coverage metricup to100%.