Research Of The Fault-tolerant Method On3D Network-on-chip Communication Architecture And Groupware

Semiconductor technology has stepped into the deep micron era. It is tendencyof integrated circuit design direction in the future. SoC in the bus-based formrestricts the modern system in design significantly. In order to improving theparallel processing capabilities of the system, An efficient communicationarchitecture on chip is very needed. So Networks-on-Chip(NoC) is put forward,which is popularly based on its good expansibility, greater throughtput and lowerpower consumption. As the growth of the IP core in a chip, however, the NoC willfaces the performance degradation, because of its long interconnect links. Thedesign method in three dimensional(3D) integrated circuits brings a new idea tointerconnect design on chip. It solves a series of problems effectively, such as thelimitation of area, interconnect delay, heterogeneous integration and so on, throughthe stacked between layer and layer. At the same time, the reliability of the chipwill be a challenge, due to TSV technology with low yield and VLSI inherentproblems. Therefore, it has become a focus of the present study to ensure3D NoCwork high reliability with a low latency.The main work of the thesis are as follows:(1)This thesis introduces the research background, key issues in researchand current research situation at home and abroad of3D NoC. Some3D NoCstructures with a high level of innovation are also detail described. In addition, thebasic knowledge, such as soft and hard failures and the corresponding fault-toleranttechnology in the3D NoC, is introduced in this thesis.(2)Considering transmission delay largely in3D NoC, a double granularitynetwork-bus hybrid architecture is presented. It reduces the delay of thecommunication of two remote nodes, using the coarse-grained network. It slovesthe delay of the communication in the close range nodes, using the fine-grainednetwork. The simulation results show that average network delay is reducedeffectively. Whenever, there is fault in the network, compared with the minTSV andISL. Besides, the system throughput is improved.(3)In view of the large area of TSV pad and the low utilization rate of TSV, acluster structure is presented, based on every four plane routers using a TSV router in a time share way. Considering the faulted plane router, the dissertation putsforward a mechanism, which the packet bypasses the faulted buffer and crossbar,according to increaseing a bypass between input and output. Besides, DEMUX andMUX controllers are added, in order to preventing the network from breakdown dueto faulted TSV router. To weaken hot spot, a novel relieved stress mechanism isproposed. It can adjust routing direction dynamically according to traffic andlocation. The simulation results show that average network delay has a differentdegree of decline, regardless a fault in the network, compared with the traditionalXYZ routing. The throughput also has a big enhancement.