Channel Decoding Technology Research Based On Microblaze Multi-core Structure

With the development of wireless communication technology, standards andprotocols are updating with each passing day. In a certain period, a variety of standardswill coexist and their own evolutions will always go on. But the Seamless Linkingunder various wireless communication environment is strongyly required by the actualapplications, which almost put the Hardware Defined Radio into a position of beingknocked out. With the fatal weakness of long development period, short life span, highcost and function unchangeableness when design is finished, Hardware Defined Radiocan hardly fulfill the rapid developing and smooth updating of the wirelesscommunication domain, then the Software Defined Radio (SDR) comes. The main ideaof SDR is mostly implementing the communication function of wireless radio bymeans of software, that is, on a general open hardware platform with standardizationand modularization, wireless communication is implemented via loading software.With the application of new technologies like MIMO、OFDM, computing volume ofbaseband processing is greatly increasing in the new generation of mobilecommunication system, which requires higher and higher system flexibility. So theresearch on the oriented IMT-Advanced common technology of baseband processing isof great value, which is significantly important for making great progress on SDRbaseband processing and realizing the smooth update in this domain.This paper focus on Microblaze-based multi-core structure channel decodingtechnology. The main contents are as following:1) Implemetation is based on Xilinx Vertex-6FPGA hardware platform, using EDKand ISE as development tools. Combining with Xilinx inter-core communicationmechanism, we designed an effective and universal multi-core parallel decodinghardware verification platform suitable for channel decoding based on twodifferent inter-core communication mechanisms (BRAM and Mailbox).2) On Microblaze multi-core parallel decoding hardware verification platformmentioned above, this paper realized dual core tail-biting convolutional decoding procedure based on WAVA parallel decomposition decoding algorithm, and testedits performance of multi-core speed-up ratio.3) On two different Microblaze multi-core parallel decoding hardware verificationplatform, this paper realized dual core tail-biting convolutional decoding procedurebased on BVA parallel decomposition decoding algorithm, and tested itsperformance of multi-core speed-up ratio.4) On Microblaze multi-core parallel decoding hardware verification platform basedon BRAM inter-core communication mechanism, this paper realized dual-core andfive-core parallel LDPC decoding procedure based on the sum-product algorithm,and tested its performance of multi-core speed-up ratio.In conclusion, the main contribution of this paper is to design and realizemulti-core parallel decoding verification platform based on BRAM and Mailboxinter-core communication mechanisms. Besides, the tail-biting convolutional code andLDPC related algorithms in multi-core decoding system are realized on the verificationplatform. Then, we verify and explain the reliability and effectiveness of decodingresults.