Design Of A Power Management Chip With Frequency Jitter And Completely Integrated Soft-start Function

Along with the rapid development of electronic technology, more and moreelectronic devices began to be used in human life. Switching power supply presents inall types of electrical as an indispensable part, and AC-DC switching powermanagement chip has been widely used because of its value of high efficiency, highintegration, small size and so on.The purpose of this project is to design a power management chip whichcompletely integrates a soft-start and frequency jitter. The main features of the chip arefrequency jitter using for reducing the chip EMI and internal integrated soft-start circuitusing for reducing device startup stress. At the same time, the chip’s internal referencemodule provides reference voltage and current which have a small temperaturecoefficient. And the chip has various protective functions, externally programmablecurrent limit and various duty cycle modulation modes.This article starts by describing the research status of the switching power supplyat home and abroad and the development trend of the switching power supplytechnology. Then combined with the power of the basic topology, the working principleof the Buck-Boost regulator is narrated emphatically, and this leads to the application ofthis chip flyback AC-DC topology. And the basic internal structure of the chip isintroduced, and how the chip peripheral application topology works is analysed.The soft-start frequency jitter module of internal modules is designed in detail. Its17ms soft-start control reduces device startup stress and limits the output overshoot.And its4ms cycle frequency jitter successfully reduces chip EMI. At the same time, thereference, gate drive, leading edge blanking, and thermal shutdown module are designed.The reference module provides a41ppm/℃reference voltage using curvaturecompensation technique and a89.4ppm/℃reference current using piecewise linearcompensation technology. The PTAT current generated by the reference module is usedto design thermal shutdown module with75℃hysteretic. By charging and dischargingof the capacitor with reference current, leading edge blanking module implements a time delay of220ns and600ns, preventing wrong turn off caused by current peakwhen turning on the power MOSFET. The gate driver module achieves the driving ofthe gate of the power MOSFET with four inverters whose drive capability increaseprogressively.The overall chip simulation focuses on changes in soft-start process of the powerMOSFET drain peak current, switching frequency and output voltage overshoot. And Isimulate in both full load condition and light load condition to verify the function offrequency jitter, the multi-cycle modulation mode and the gate voltage of powerMOSFET. And under different operating conditions, the output voltage can be stablymaintained at12V, which meets the design requirement.