FPGA Design And System Verification Of The Digital If Receiver Based On128QAM

With the development of communication technology，more and more attention ispaid to the high-speed and high-capacity communication data transmission, meanwhile,the interconnection between the different means of communication has becomeparticularly complex and difficult. Since mutually independent data processed clocksare used in the transmitting end and the receiving end, the all-digital modulation anddemodulation techniques well process high-speed data transmission. At the same time inconjunction with multi-band signal modulation method, the all-digital modulation anddemodulation techniques have greatly improved the transmission capacity of the data,so as to effectively solve the modern communication problem of data transmission. Thesoftware radio technology makes multi-band, multi-mode, multi-function wirelesstransmission equipments communicate with each other and allows the transmission datato have a large bandwidth. Therefore it is gradually applied in the field of civilcommunication to solve interconnection problems between different means ofcommunication in the modern communication.Under the request in the research, the information transmission rate is up to100Mbps, the signal bandwidth is no more than28MHz, the information error rate is nomore than1×10^-3under the SNR of23dB， and the system transmission delay is nomore than50us. This paper, using M-QAM signal modulation and demodulationtechniques, designs and achieves a digital IF receiver system based on FPGA. Thissystem uses a software radio architecture of the broadband IF band-pass sampling, andprocesses the received signal by all-digital demodulation. The main work is as follows:1) According to the subject designed requirements, design the sampling frequencyof ADC isf_S=76.8MHz, the symbol rate is19.2MBps, after DUC the intermediatefrequency is96MHz, the channel coding scheme of sending signal is RS（31,27）, theroll-off factor of the sending signal shaping filter is0.12.2) Explain the project design in detail, and give a detailed algorithm descriptionand simulation to each unit of eliminating signal error in the system. Timingsynchronization unit uses the improved Gardner algorithm to extract the signal sampled error, which is corrected by the phase comparison method. Channel equalization unituses the constant modulus algorithm, a blind equalization algorithm based on Bussgangalgorithm, to correct the amplitude attenuation of the received signal. Carriersynchronization unit uses the polarity decision algorithm, a mode conversion carriererror correction algorithm, to eliminate the signal phase errors caused by the all-digitaldemodulation.3) Introduce the software radio platform, and according to the designed systemsolution, give a specific structure of the system implementation based on FPGA. Themain function modules inside the receiver are given a detailed description ofprogramming and achieving. At the same time, each module has been given a compilereport and a timing constraints report, and simulated in Modelsim, all the results ofwhich prove the module is required to achieve. At last, load the entire system moduleinto the software radio platform, and obtain the experimental data by SignalTapⅡ,which has verified the correctness and reliability practicability of the project. At thetime, it is obtained that the system transmission delay, which is4us and meets therequirements of subject design.