0.18 Um Design And Implementation Of The Fpga Programmable Logic Unit

FPGA can reduce the NRE (Non-Recurring Engineering) cost, design risk, Time-to-Market and maintenance cost of electronic system. So it’s widely used in electronic systems. The CLB(Configurable Logic Block) is a very important part in FPGA chip. All the combinational and sequential logics are achieved by it. So we must place much more emphasis on it’s design.This thesis works on the research of the CLB in FPGA based on LUT. In this thesis we propose the design thought and detailed circuit to achieve the function of the distributed RAM and the shift register;save some area by combining their sequential control modules into one;expend the logic of the carry chain including achieving the function of multipliers,counters and "big AND(OR)" logic conveniently,design the circuits of capturing and writing back the DFF data in CLB in order to support the function of reconfiguration;propose the design idea,detailed circuit,modeling and simulation method of some important modules such as level shifter and MOS SRAM cell;simulate the functions and the performances of the entire CLB using HSPICE.Based on the SM1C 0.18um Logic 1P6M Salicide 1.8V/3.3V technology and full-custom circuit design methodology, we have finished the layout design of the FPGA chip (named FDP1000K) and have sent it out to tape out. The chip includes 1200 programmable logic slices, 240 user I/Os, ten 4K bits block RAMs,and 1000,000 equivalent system gates.